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authorJosh Blum <josh@joshknows.com>2012-03-01 19:59:10 -0800
committerJosh Blum <josh@joshknows.com>2012-03-16 11:29:17 -0700
commit0d712ac8ac311f716bb6fc418a46abb79c71e3b4 (patch)
tree8a39f5b5850af4b4f0899dc130607ef9652a7892 /usrp2/control_lib
parentd6da6c4145d4f7411004e0c8176f029cbe998c09 (diff)
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fifo_ctrl: clear settings reg, and flow control
Diffstat (limited to 'usrp2/control_lib')
-rw-r--r--usrp2/control_lib/settings_bus_crossclock.v9
-rw-r--r--usrp2/control_lib/settings_readback_bus_fifo_ctrl.v3
2 files changed, 7 insertions, 5 deletions
diff --git a/usrp2/control_lib/settings_bus_crossclock.v b/usrp2/control_lib/settings_bus_crossclock.v
index 9c5912042..a61ee8fad 100644
--- a/usrp2/control_lib/settings_bus_crossclock.v
+++ b/usrp2/control_lib/settings_bus_crossclock.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -22,16 +22,17 @@
// the system or dsp clock on the output side
module settings_bus_crossclock
+ #(parameter FLOW_CTRL=0)
(input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i,
- input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o);
+ input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o, input blocked);
wire full, empty;
fifo_xlnx_16x40_2clk settings_fifo
(.rst(rst_i),
.wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full),
- .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(~empty), .empty(empty));
+ .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(set_stb_o), .empty(empty));
- assign set_stb_o = ~empty;
+ assign set_stb_o = ~empty & (~blocked | ~FLOW_CTRL);
endmodule // settings_bus_crossclock
diff --git a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
index 89efd2203..24c618d79 100644
--- a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
+++ b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
@@ -251,7 +251,8 @@ module settings_readback_bus_fifo_ctrl
end
WAIT_CMD: begin
- if (now || late) out_state <= ACTION_EVENT;
+ if (clear) out_state <= LOAD_CMD;
+ else if (now || late) out_state <= ACTION_EVENT;
end
ACTION_EVENT: begin // poking and peeking happens here!