fifo ctrl: simplified perfs, added spi clock idle phase

2 files changed, 21 insertions, 13 deletions

diff --git a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
index 18119d2bd..f99d3969d 100644
--- a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
+++ b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
@@ -19,7 +19,6 @@
 
 module settings_readback_bus_fifo_ctrl
     #(
-        parameter NUM_PERFS = 4,
         parameter FIFO_DEPTH = 6, //64 entries depth
         parameter PROT_DEST = 0 //protocol framer destination
     )
@@ -30,8 +29,8 @@ module settings_readback_bus_fifo_ctrl
         //current system time
         input [63:0] vita_time,
 
-        //ready signals for multiple peripherals
-        input [NUM_PERFS-1:0] perfs_ready,
+        //ready signal for multiple peripherals
+        input perfs_ready,
 
         //input fifo36 interface control
         input [35:0] in_data, input in_valid, output in_ready,
@@ -248,12 +247,10 @@ module settings_readback_bus_fifo_ctrl
     `endif
 
     //action occurs in the event state and when there is fifo space (should always be true)
-    //the third condition is that all peripherals in the mask are ready/active high
+    //the third condition is that all peripherals in the perfs signal are ready/active high
     //the fourth condition is that is an event time has been set, action is delayed until that time
-    wire [NUM_PERFS-1:0] perfs_mask = command_hdr_reg[10+NUM_PERFS-1:10];
-    wire perfs_in_mask_ready = (perfs_ready & perfs_mask) == perfs_mask;
-    wire time_ready = (out_command_has_time)? (now || late || clear) : 1;
-    wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_in_mask_ready && time_ready;
+    wire time_ready = (out_command_has_time)? (now || late) : 1;
+    wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready;
 
     assign command_fifo_read = action;
     assign result_fifo_write = action;
@@ -275,7 +272,7 @@ module settings_readback_bus_fifo_ctrl
             end
 
             EVENT_CMD: begin // poking and peeking happens here!
-                if (action) cmd_state <= LOAD_CMD;
+                if (action || clear) cmd_state <= LOAD_CMD;
             end
 
             endcase //cmd_state
diff --git a/usrp2/control_lib/simple_spi_core.v b/usrp2/control_lib/simple_spi_core.v
index dbfa5ad8b..31bc26f95 100644
--- a/usrp2/control_lib/simple_spi_core.v
+++ b/usrp2/control_lib/simple_spi_core.v
@@ -101,17 +101,20 @@ module simple_spi_core
     localparam CLK_REG = 2;
     localparam CLK_INV = 3;
     localparam POST_IDLE = 4;
+    localparam IDLE_SEN = 5;
 
     reg [2:0] state;
 
-    assign ready = (state == WAIT_TRIG);
+    reg ready_reg;
+    assign ready = ready_reg;
 
     //serial clock either idles or is in one of two clock states
     reg sclk_reg;
     assign sclk = sclk_reg;
 
     //serial enables either idle or enabled based on state
-    wire [23:0] sen24 = (ready)? SEN_IDLE : (SEN_IDLE ^ slave_select);
+    wire sen_is_idle = (state == WAIT_TRIG) || (state == IDLE_SEN);
+    wire [23:0] sen24 = (sen_is_idle)? SEN_IDLE : (SEN_IDLE ^ slave_select);
     reg [WIDTH-1:0] sen_reg;
     always @(posedge clock) sen_reg <= sen24[WIDTH-1:0];
     assign sen = sen_reg;
@@ -140,21 +143,23 @@ module simple_spi_core
         if (reset) begin
             state <= WAIT_TRIG;
             sclk_reg <= CLK_IDLE;
+            ready_reg <= 0;
         end
         else begin
             case (state)
 
             WAIT_TRIG: begin
                 if (trigger_spi) state <= PRE_IDLE;
+                ready_reg <= ~trigger_spi;
+                dataout_reg <= mosi_data;
                 sclk_counter <= 0;
+                bit_counter <= 0;
                 sclk_reg <= CLK_IDLE;
             end
 
             PRE_IDLE: begin
                 if (sclk_counter_done) state <= CLK_REG;
                 sclk_counter <= sclk_counter_next;
-                dataout_reg <= mosi_data;
-                bit_counter <= 0;
                 sclk_reg <= CLK_IDLE;
             end
 
@@ -180,6 +185,12 @@ module simple_spi_core
             end
 
             POST_IDLE: begin
+                if (sclk_counter_done) state <= IDLE_SEN;
+                sclk_counter <= sclk_counter_next;
+                sclk_reg <= CLK_IDLE;
+            end
+
+            IDLE_SEN: begin
                 if (sclk_counter_done) state <= WAIT_TRIG;
                 sclk_counter <= sclk_counter_next;
                 sclk_reg <= CLK_IDLE;