Merge branch 'udp' into master_merge_take2

* udp: (67 commits)
  better test program for just the tx side
  fix typo, no functionality difference
  ignores
  move dsp settings regs to reclocked setting bus.  Works, gets us to within 18ps of passing timing
  reverting logic clean up which should have made timing better, but made it worse instead
  moved fifos around, now easier to see where they are and how big
  bigger fifo on UDP TX path, to possibly fix overruns on decim=4
  Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround
  pps and vita time debug pins
  ignore emacs backup files
  more debug for fixing E's
  better debug pins for going after cascading E's
  copy in wrong place
  copied over from quad radio
  just debug pin changes
  typo caused the tx udp chain to be disconnected
  moved into subdir
  speed up timing by ignoring the too_early error.  We'll need to FIXME this later
  Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore.
  moved around regs, added a bit to allow for alternate PPS source
  ...

3 files changed, 49 insertions, 49 deletions

diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
index e22ca0a49..5f9aeff9b 100644
--- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
+++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
@@ -7,7 +7,8 @@ module fifo19_to_fifo36
 
    output [35:0] f36_dataout,
    output f36_src_rdy_o,
-   input f36_dst_rdy_i
+   input f36_dst_rdy_i,
+   output [31:0] debug
    );
 
    reg 	 f36_sof, f36_eof, f36_occ;
@@ -50,7 +51,9 @@ module fifo19_to_fifo36
 	     state <= 2;
 	   2 : 
 	     if(xfer_out)
-	       state 	   <= 1;
+	       if(~f19_eof)
+		 state 	   <= 1;
+	   // remain in state 2 if we are at eof
 	 endcase // case(state)
        else
 	 if(xfer_out)
@@ -67,5 +70,7 @@ module fifo19_to_fifo36
    assign    f19_dst_rdy_o  = xfer_out | (state != 2);
    assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
    assign    f36_src_rdy_o  = (state == 2);
-      
+
+   assign    debug = state;
+   
 endmodule // fifo19_to_fifo36
diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo19.v b/usrp2/control_lib/newfifo/ll8_to_fifo19.v
index c65be5136..af3b91afb 100644
--- a/usrp2/control_lib/newfifo/ll8_to_fifo19.v
+++ b/usrp2/control_lib/newfifo/ll8_to_fifo19.v
@@ -10,68 +10,64 @@ module ll8_to_fifo19
    output [18:0] f19_data,
    output f19_src_rdy_o,
    input f19_dst_rdy_i );
-
+   
+   localparam XFER_EMPTY       = 0;
+   localparam XFER_HALF        = 1;
+   localparam XFER_HALF_WRITE  = 3;
+   
    // Why anybody would use active low in an FPGA is beyond me...
    wire  ll_sof      = ~ll_sof_n;
    wire  ll_eof      = ~ll_eof_n;
    wire  ll_src_rdy  = ~ll_src_rdy_n;
    wire  ll_dst_rdy;
    assign    ll_dst_rdy_n  = ~ll_dst_rdy;
-
-   wire xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
-   //  wire xfer_in 	   = ll_src_rdy & ll_dst_rdy;   Not needed
    
-   reg 	 f19_sof, f19_eof, f19_occ;
+   wire  xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire  xfer_in 	   = ll_src_rdy & ll_dst_rdy; 
+   
+   reg 	 hold_sof;
+   wire  f19_sof, f19_eof, f19_occ;
    
    reg [1:0] state;
-   reg [7:0] dat0, dat1;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state==0)|xfer_out))
-       f19_sof <= ll_sof;
-
+   reg [7:0] hold_reg;
+   
    always @(posedge clk)
-     if(ll_src_rdy & ((state != 2)|xfer_out))
-       f19_eof <= ll_eof;
-
+     if(ll_src_rdy & (state==XFER_EMPTY))
+       hold_reg 	      <= ll_data;
+   
    always @(posedge clk)
-     if(ll_eof)
-       f19_occ <= ~state[0];
-     else
-       f19_occ <= 0;
+     if(ll_sof & (state==XFER_EMPTY))
+       hold_sof 	      <= 1;
+     else if(xfer_out)
+       hold_sof 	      <= 0;
    
    always @(posedge clk)
-     if(reset)
-       state   <= 0;
+     if(reset | clear)
+       state 		      <= XFER_EMPTY;
      else
-       if(ll_src_rdy)
-	 case(state)
-	   0 : 
+       case(state)
+	 XFER_EMPTY :
+	   if(ll_src_rdy)
 	     if(ll_eof)
-	       state <= 2;
+	       state 	      <= XFER_HALF_WRITE;
 	     else
-	       state <= 1;
-	   1 : 
-	     state <= 2;
-	   2 : 
-	     if(xfer_out)
-	       state 	   <= 1;
-	 endcase // case(state)
-       else
-	 if(xfer_out)
-	   state 	   <= 0;
-
-   always @(posedge clk)
-     if(ll_src_rdy & (state==1))
-       dat1 		   <= ll_data;
-
-   always @(posedge clk)
-     if(ll_src_rdy & ((state==0) | xfer_out))
-       dat0 		   <= ll_data;
+	       state 	      <= XFER_HALF;
+	 XFER_HALF :
+	   if(ll_src_rdy & f19_dst_rdy_i)
+	       state 	      <= XFER_EMPTY;
+         XFER_HALF_WRITE :
+	   if(f19_dst_rdy_i)
+	     state 	<= XFER_EMPTY;
+       endcase // case (state)
+      
+   assign ll_dst_rdy 	 = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i);
+   assign f19_src_rdy_o  = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy);
+   
+   assign f19_sof 	 = hold_sof | (ll_sof & (state==XFER_HALF));
+   assign f19_eof 	 = (state == XFER_HALF_WRITE) | ll_eof;
+   assign f19_occ 	 = (state == XFER_HALF_WRITE);
    
-   assign    ll_dst_rdy     = xfer_out | (state != 2);
-   assign    f19_data 	    = {f19_occ,f19_eof,f19_sof,dat0,dat1};
-   assign    f19_src_rdy_o  = (state == 2);
+   assign f19_data 	 = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
       
 endmodule // ll8_to_fifo19
 
diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v
index d01a30ab4..fc960e456 100644
--- a/usrp2/control_lib/settings_bus.v
+++ b/usrp2/control_lib/settings_bus.v
@@ -10,7 +10,6 @@ module settings_bus
      input wb_stb_i,
      input wb_we_i,
      output reg wb_ack_o,
-     input sys_clk,
      output strobe,
      output reg [7:0] addr,
      output reg [31:0] data);