Merge branch 'gpmc_testing' into ethfifo_reorg

* gpmc_testing:
  timed packet generator : Temporarily use a checksum rather than a crc to validate packet integrity.
  correct port names
  fifo36_mux now has shortfifos on the input ports as well as output
  timed tester : Bring out src/dst flags for rx chain for testing.
  u1e: hook up tester controls
  move declarations to before use
  hook up under/overruns for debug purposes
  e100: integrate loopback and timed testing into main image
  Fix endianess for packet length and sequence number for e100 timed image.
  put these files in the right place.  newfifo is long gone.

8 files changed, 0 insertions, 256 deletions

diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
index 5ae185ee8..751b40828 100644
--- a/usrp2/control_lib/Makefile.srcs
+++ b/usrp2/control_lib/Makefile.srcs
@@ -50,9 +50,4 @@ bootram.v \
 nsgpio16LE.v \
 settings_bus_16LE.v \
 atr_controller16.v \
-newfifo/fifo_pacer.v \
-newfifo/packet_generator32.v \
-newfifo/packet_generator.v \
-newfifo/packet_verifier32.v \
-newfifo/packet_verifier.v \
 ))
diff --git a/usrp2/control_lib/newfifo/fifo_pacer.v b/usrp2/control_lib/newfifo/fifo_pacer.v
deleted file mode 100644
index 1bf03ab6e..000000000
--- a/usrp2/control_lib/newfifo/fifo_pacer.v
+++ /dev/null
@@ -1,24 +0,0 @@
-
-
-module fifo_pacer
-  (input clk,
-   input reset,
-   input [7:0] rate,
-   input enable,
-   input src1_rdy_i, output dst1_rdy_o,
-   output src2_rdy_o, input dst2_rdy_i,
-   output underrun, overrun);
-
-   wire   strobe;
-   
-   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
-			.rate(rate), .strobe_fast(1), .strobe_slow(strobe));
-
-   wire   all_ready = src1_rdy_i & dst2_rdy_i;
-   assign dst1_rdy_o = all_ready & strobe;
-   assign src2_rdy_o = dst1_rdy_o;
-
-   assign underrun = strobe & ~src1_rdy_i;
-   assign overrun = strobe & ~dst2_rdy_i;
-   
-endmodule // fifo_pacer
diff --git a/usrp2/control_lib/newfifo/packet32_tb.v b/usrp2/control_lib/newfifo/packet32_tb.v
deleted file mode 100644
index 82bb09c29..000000000
--- a/usrp2/control_lib/newfifo/packet32_tb.v
+++ /dev/null
@@ -1,27 +0,0 @@
-
-
-module packet32_tb();
-
-   wire [35:0] data;
-   wire       src_rdy, dst_rdy;
-
-   wire       clear = 0;
-   reg 	      clk = 0;
-   reg 	      reset = 1;
-
-   always #10 clk <= ~clk;
-   initial #1000 reset <= 0;
-
-   initial $dumpfile("packet32_tb.vcd");
-   initial $dumpvars(0,packet32_tb);
-
-   wire [31:0] total, crc_err, seq_err, len_err;
-   
-   packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
-			       .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
-
-   packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
-			      .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
-			      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
-endmodule // packet32_tb
diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v
deleted file mode 100644
index 6e8b45ccd..000000000
--- a/usrp2/control_lib/newfifo/packet_generator.v
+++ /dev/null
@@ -1,59 +0,0 @@
-
-
-module packet_generator
-  (input clk, input reset, input clear,
-   output reg [7:0] data_o, output sof_o, output eof_o, 
-   output src_rdy_o, input dst_rdy_i);
-
-   localparam len = 32'd2000;
-
-   reg [31:0] state;
-   reg [31:0] seq;
-   wire [31:0] crc_out;
-   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
-   
-	
-   always @(posedge clk)
-     if(reset | clear)
-       seq <= 0;
-     else
-       if(eof_o & src_rdy_o & dst_rdy_i)
-	 seq <= seq + 1;
-   
-   always @(posedge clk)
-     if(reset | clear)
-       state <= 0;
-     else
-       if(src_rdy_o & dst_rdy_i)
-	 if(state == (len - 1))
-	   state <= 32'hFFFF_FFFC;
-	 else
-	   state <= state + 1;
-
-   always @*
-     case(state)
-       0 :   data_o <= len[7:0];
-       1 :   data_o <= len[15:8];
-       2 :   data_o <= len[23:16];
-       3 :   data_o <= len[31:24];
-       4 :   data_o <= seq[7:0];
-       5 :   data_o <= seq[15:8];
-       6 :   data_o <= seq[23:16];
-       7 :   data_o <= seq[31:24];
-       32'hFFFF_FFFC : data_o <= crc_out[31:24];
-       32'hFFFF_FFFD : data_o <= crc_out[23:16];
-       32'hFFFF_FFFE : data_o <= crc_out[15:8];
-       32'hFFFF_FFFF : data_o <= crc_out[7:0];
-       default : data_o <= state[7:0];
-     endcase // case (state)
-   
-   assign src_rdy_o = 1;
-   assign sof_o = (state == 0);
-   assign eof_o = (state == 32'hFFFF_FFFF);
-
-   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
-   
-   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
-	   .calc(calc_crc), .crc_out(crc_out), .match());
-   
-endmodule // packet_generator
diff --git a/usrp2/control_lib/newfifo/packet_generator32.v b/usrp2/control_lib/newfifo/packet_generator32.v
deleted file mode 100644
index 6f8004964..000000000
--- a/usrp2/control_lib/newfifo/packet_generator32.v
+++ /dev/null
@@ -1,21 +0,0 @@
-
-
-module packet_generator32
-  (input clk, input reset, input clear,
-   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
-
-   wire [7:0] 	     ll_data;
-   wire 	     ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n;
-   
-   packet_generator pkt_gen
-     (.clk(clk), .reset(reset), .clear(clear),
-      .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
-      .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
-
-   ll8_to_fifo36 ll8_to_f36
-     (.clk(clk), .reset(reset), .clear(clear),
-      .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof),
-      .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n),
-      .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i));
-   
-endmodule // packet_generator32
diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/control_lib/newfifo/packet_tb.v
deleted file mode 100644
index 3c423d2ba..000000000
--- a/usrp2/control_lib/newfifo/packet_tb.v
+++ /dev/null
@@ -1,29 +0,0 @@
-
-
-module packet_tb();
-
-   wire [7:0] data;
-   wire       sof, eof, src_rdy, dst_rdy;
-
-   wire       clear = 0;
-   reg 	      clk = 0;
-   reg 	      reset = 1;
-
-   always #10 clk <= ~clk;
-   initial #1000 reset <= 0;
-
-   initial $dumpfile("packet_tb.vcd");
-   initial $dumpvars(0,packet_tb);
-
-   wire [31:0] total, crc_err, seq_err, len_err;
-   
-   packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
-			     .data_o(data), .sof_o(sof), .eof_o(eof),
-			     .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
-
-   packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
-			    .data_i(data), .sof_i(sof), .eof_i(eof),
-			    .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
-			    .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
-endmodule // packet_tb
diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v
deleted file mode 100644
index b49ad1bbb..000000000
--- a/usrp2/control_lib/newfifo/packet_verifier.v
+++ /dev/null
@@ -1,61 +0,0 @@
-
-
-// Packet format --
-//    Line 1 -- Length, 32 bits
-//    Line 2 -- Sequence number, 32 bits
-//    Last line -- CRC, 32 bits
-
-module packet_verifier
-  (input clk, input reset, input clear,
-   input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o,
-
-   output reg [31:0] total, 
-   output reg [31:0] crc_err, 
-   output reg [31:0] seq_err, 
-   output reg [31:0] len_err);
-
-   reg [31:0] 	     seq_num;
-   reg [31:0] 	     length;
-   wire 	     first_byte, last_byte;
-   reg 		     second_byte, last_byte_d1;
-
-   wire 	     calc_crc = src_rdy_i & dst_rdy_o;
-   
-   crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
-	   .calc(calc_crc), .crc_out(), .match(match_crc));
-
-   assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
-   assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
-   assign dst_rdy_o = ~last_byte_d1;
-
-   // stubs for now
-   wire 	     match_seq = 1;
-   wire 	     match_len = 1;
-   
-   always @(posedge clk)
-     if(reset | clear)
-       last_byte_d1 <= 0;
-     else 
-       last_byte_d1 <= last_byte;
-
-   always @(posedge clk)
-     if(reset | clear)
-       begin
-	  total <= 0;
-	  crc_err <= 0;
-	  seq_err <= 0;
-	  len_err <= 0;
-       end
-     else
-       if(last_byte_d1)
-	 begin
-	    total <= total + 1;
-	    if(~match_crc)
-	      crc_err <= crc_err + 1;
-	    else if(~match_seq)
-	      seq_err <= seq_err + 1;
-	    else if(~match_len)
-	      seq_err <= len_err + 1;
-	 end
-   
-endmodule // packet_verifier
diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v
deleted file mode 100644
index 06a13d242..000000000
--- a/usrp2/control_lib/newfifo/packet_verifier32.v
+++ /dev/null
@@ -1,30 +0,0 @@
-
-
-module packet_verifier32
-  (input clk, input reset, input clear,
-   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
-   output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err);
-
-   wire [7:0] 	     ll_data;
-   wire 	     ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy;
-   wire [35:0] 	     data_int;
-   wire 	     src_rdy_int, dst_rdy_int;
-   
-   fifo_short #(.WIDTH(36)) fifo_short
-     (.clk(clk), .reset(reset), .clear(clear),
-      .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
-      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));
-   
-   fifo36_to_ll8 f36_to_ll8
-     (.clk(clk), .reset(reset), .clear(clear),
-      .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
-      .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n),
-      .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy));
-   
-   packet_verifier pkt_ver
-     (.clk(clk), .reset(reset), .clear(clear),
-      .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n),
-      .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy),
-      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
-endmodule // packet_verifier32