removed wb readback of ATR, allowing it to be synthesized as luts

2 files changed, 10 insertions, 4 deletions

diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v
index 2cef8ba2b..1f8d75d00 100644
--- a/usrp2/control_lib/atr_controller.v
+++ b/usrp2/control_lib/atr_controller.v
@@ -44,8 +44,11 @@ module atr_controller
 	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
        end // if (we_i & stb_i & cyc_i)
 
-   always @(posedge clk_i)
-     dat_o <= atr_ram[adr_i[5:2]];
+   // Removing readback allows ram to be synthesized as LUTs instead of regs
+   //always @(posedge clk_i)
+   //  dat_o <= atr_ram[adr_i[5:2]];
+   always @*
+     dat_o <= 32'd0;
    
    always @(posedge clk_i)
      ack_o <= stb_i & cyc_i & ~ack_o;
diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v
index ff4f634c7..a2ebd1dde 100644
--- a/usrp2/control_lib/atr_controller16.v
+++ b/usrp2/control_lib/atr_controller16.v
@@ -47,8 +47,11 @@ module atr_controller16
 	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
        end // if (we_i & stb_i & cyc_i)
 
-   always @(posedge clk_i)
-     dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+   // Removing readback allows ram to be synthesized as LUTs instead of regs
+   //always @(posedge clk_i)
+   //  dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+   always @*
+     dat_o <= 16'd0;
    
    always @(posedge clk_i)
      ack_o <= stb_i & cyc_i & ~ack_o;