Merge branch 'u1e' into merge_u1e

* u1e: (130 commits)
  invert led signals because they are active low
  duh
  allow for CS to rise before, at the same time, or after OE
  better debug pins
  watch the ethernet chip select on our debug bus
  fix timing issue on DAC outputs with rev 2.  This puts the whole system on a 90 degree phase shift
  send all gpmc signals to mictor
  updated pins to match rev2, removed dip switch, etc.  seems to compile ok.
  pins are different on rev2
  fixed makefile to compile with our new system
  add register to tell host about compatibility level and which image we are using
  move declaration to make loopback compile
  no need for protocol headers since we're not doing ethernet
  match the signal names in this design
  debug pins cleanup
  properly integrate the new tx chain
  catch up with tx_policy
  attach run_tx and run_rx to leds
  connect atr
  delay the q channel to make the channels line up on the AD9862
  ...

Conflicts:
	usrp2/control_lib/Makefile.srcs

1 files changed, 54 insertions, 0 deletions

diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v
new file mode 100644
index 000000000..76061e9e0
--- /dev/null
+++ b/usrp2/control_lib/settings_bus_16LE.v
@@ -0,0 +1,54 @@
+
+// Grab settings off the wishbone bus, send them out to settings bus
+// 16 bits little endian, but all registers need to be written 32 bits at a time.
+// This means that you write the low 16 bits first and then the high 16 bits.
+// The setting regs are strobed when the high 16 bits are written
+
+module settings_bus_16LE
+  #(parameter AWIDTH=16, RWIDTH=8)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [15:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     output strobe,
+     output reg [7:0] addr,
+     output reg [31:0] data);
+
+   reg 		       stb_int;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  stb_int <= 1'b0;
+	  addr <= 8'd0;
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i)
+       begin
+	  addr <= wb_adr_i[RWIDTH+1:2];  // Zero pad high bits
+	  if(wb_adr_i[1])
+	    begin
+	       stb_int <= 1'b1;     // We now have both halves
+	       data[31:16] <= wb_dat_i;
+	    end
+	  else
+	    begin
+	       stb_int <= 1'b0;     // Don't strobe, we need other half
+	       data[15:0] <= wb_dat_i;
+	    end
+       end
+     else
+       stb_int <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+   assign strobe = stb_int & wb_ack_o;
+          
+endmodule // settings_bus_16LE