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author | Matt Ettus <matt@ettus.com> | 2010-03-25 21:00:25 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-03-25 21:00:25 -0700 |
commit | f979a9d4e7b9664e046aaca54357e46782c4aa51 (patch) | |
tree | d48bb446844d647977c2ba4d52fcb64d935df079 /usrp2/control_lib/setting_reg.v | |
parent | b74388567c0ed3048e45158ac077e31def59fea1 (diff) | |
parent | 16818dc98e97b69a028c47e66ebfb16e32565533 (diff) | |
download | uhd-f979a9d4e7b9664e046aaca54357e46782c4aa51.tar.gz uhd-f979a9d4e7b9664e046aaca54357e46782c4aa51.tar.bz2 uhd-f979a9d4e7b9664e046aaca54357e46782c4aa51.zip |
Merge branch 'udp' into u1e
Diffstat (limited to 'usrp2/control_lib/setting_reg.v')
-rw-r--r-- | usrp2/control_lib/setting_reg.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v index ccbaa3d2e..c8aff230f 100644 --- a/usrp2/control_lib/setting_reg.v +++ b/usrp2/control_lib/setting_reg.v @@ -1,14 +1,14 @@ module setting_reg - #(parameter my_addr = 0) + #(parameter my_addr = 0, parameter at_reset=32'd0) (input clk, input rst, input strobe, input wire [7:0] addr, input wire [31:0] in, output reg [31:0] out, output reg changed); always @(posedge clk) if(rst) begin - out <= 32'd0; + out <= at_reset; changed <= 1'b0; end else |