Moved usrp2 fpga files into usrp2 subdir.

1 files changed, 16 insertions, 0 deletions

diff --git a/usrp2/control_lib/reset_sync.v b/usrp2/control_lib/reset_sync.v
new file mode 100644
index 000000000..94d966840
--- /dev/null
+++ b/usrp2/control_lib/reset_sync.v
@@ -0,0 +1,16 @@
+
+
+module reset_sync
+  (input clk,
+   input reset_in,
+   output reg reset_out);
+
+   reg 	      reset_int;
+
+   always @(posedge clk or posedge reset_in)
+     if(reset_in)
+       {reset_out,reset_int} <= 2'b11;
+     else
+       {reset_out,reset_int} <= {reset_int,1'b0};
+   
+endmodule // reset_sync