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| author | Josh Blum <josh@joshknows.com> | 2011-08-18 16:42:26 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-26 13:23:21 -0700 |
| commit | d5cbb77380d8f408469735b6ed6d4e10763d63b2 (patch) | |
| tree | 312ee01ad316d495be65d6aa7b4860652732816c /usrp2/control_lib/bootram.v | |
| parent | ccafda72b4d1acf820be26e488bbfc530ca31c65 (diff) | |
| download | uhd-d5cbb77380d8f408469735b6ed6d4e10763d63b2.tar.gz uhd-d5cbb77380d8f408469735b6ed6d4e10763d63b2.tar.bz2 uhd-d5cbb77380d8f408469735b6ed6d4e10763d63b2.zip | |
usrp2: reconnect frontend calibration, timing meets
Diffstat (limited to 'usrp2/control_lib/bootram.v')
| -rw-r--r-- | usrp2/control_lib/bootram.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index fb7bd46c8..135ebad73 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -83,7 +83,7 @@ module bootram .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -93,7 +93,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB0), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input |