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| author | Matt Ettus <matt@ettus.com> | 2011-07-19 10:29:57 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-07-19 13:49:17 -0700 |
| commit | dbeea34b66c939c15eaaa0a9f805ee9286d0a878 (patch) | |
| tree | d3759ecadeb4545946db3e58a45035ec74022e75 /usrp2/control_lib/atr_controller.v | |
| parent | 374bf86dd1d11dd4165c8da0ce317194d17ba89a (diff) | |
| download | uhd-dbeea34b66c939c15eaaa0a9f805ee9286d0a878.tar.gz uhd-dbeea34b66c939c15eaaa0a9f805ee9286d0a878.tar.bz2 uhd-dbeea34b66c939c15eaaa0a9f805ee9286d0a878.zip | |
removed wb readback of ATR, allowing it to be synthesized as luts
Diffstat (limited to 'usrp2/control_lib/atr_controller.v')
| -rw-r--r-- | usrp2/control_lib/atr_controller.v | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v index 2cef8ba2b..1f8d75d00 100644 --- a/usrp2/control_lib/atr_controller.v +++ b/usrp2/control_lib/atr_controller.v @@ -44,8 +44,11 @@ module atr_controller atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; end // if (we_i & stb_i & cyc_i) - always @(posedge clk_i) - dat_o <= atr_ram[adr_i[5:2]]; + // Removing readback allows ram to be synthesized as LUTs instead of regs + //always @(posedge clk_i) + // dat_o <= atr_ram[adr_i[5:2]]; + always @* + dat_o <= 32'd0; always @(posedge clk_i) ack_o <= stb_i & cyc_i & ~ack_o; |