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| author | Matt Ettus <matt@ettus.com> | 2010-06-14 13:23:18 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-06-14 13:23:18 -0700 |
| commit | a97707caa8e9f19fdc81061ac11a73f41aab2704 (patch) | |
| tree | c75983a4caff316fe1c64cdba047229ac4584cc7 /usrp2/control_lib/Makefile.srcs | |
| parent | a4b11332ab4f6a24bf4645c0b2770f9578a36f45 (diff) | |
| parent | 9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff) | |
| download | uhd-a97707caa8e9f19fdc81061ac11a73f41aab2704.tar.gz uhd-a97707caa8e9f19fdc81061ac11a73f41aab2704.tar.bz2 uhd-a97707caa8e9f19fdc81061ac11a73f41aab2704.zip | |
Merge branch 'master' into u1e_newbuild
Made so Makefile changes as well to get it to build
* master:
new make works on ise12
produces good bin files
first attempt at cleaning up the build system
get rid of debug stuff to help timing
move u2_core into u2_rev3 directory to simplify directory structure and save headaches
Conflicts:
usrp2/fifo/fifo36_to_fifo18.v
usrp2/top/u2_rev3/Makefile
usrp2/top/u2_rev3/Makefile.udp
usrp2/top/u2_rev3/u2_core_udp.v
Diffstat (limited to 'usrp2/control_lib/Makefile.srcs')
| -rw-r--r-- | usrp2/control_lib/Makefile.srcs | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs new file mode 100644 index 000000000..095890d59 --- /dev/null +++ b/usrp2/control_lib/Makefile.srcs @@ -0,0 +1,47 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# Control Lib Sources +################################################## +CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../control_lib/, \ +CRC16_D16.v \ +atr_controller.v \ +bin2gray.v \ +dcache.v \ +decoder_3_8.v \ +dpram32.v \ +gray2bin.v \ +gray_send.v \ +icache.v \ +mux4.v \ +mux8.v \ +nsgpio.v \ +ram_2port.v \ +ram_harv_cache.v \ +ram_loader.v \ +setting_reg.v \ +settings_bus.v \ +settings_bus_crossclock.v \ +srl.v \ +system_control.v \ +wb_1master.v \ +wb_readback_mux.v \ +simple_uart.v \ +simple_uart_tx.v \ +simple_uart_rx.v \ +oneshot_2clk.v \ +sd_spi.v \ +sd_spi_wb.v \ +wb_bridge_16_32.v \ +reset_sync.v \ +priority_enc.v \ +pic.v \ +longfifo.v \ +shortfifo.v \ +medfifo.v \ +nsgpio16LE.v \ +settings_bus_16LE.v \ +atr_controller16.v \ +)) |