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authorMatt Ettus <matt@ettus.com>2010-06-14 11:59:19 -0700
committerMatt Ettus <matt@ettus.com>2010-06-14 11:59:19 -0700
commit81ad405f9ddecf13e1238bdc53a251b0b71022b5 (patch)
tree999d7ebf90ad86e8e56aa8f06a44d5b74fa4833f /usrp2/control_lib/Makefile.srcs
parentfb704918b285a7d039cda27daf35f628442a7dca (diff)
parent1935f2a4ed0d0abc90bb3fe7fed745ff84ab6d7c (diff)
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Merge branch 'master' into u2p
* master: produces good bin files first attempt at cleaning up the build system
Diffstat (limited to 'usrp2/control_lib/Makefile.srcs')
-rw-r--r--usrp2/control_lib/Makefile.srcs44
1 files changed, 44 insertions, 0 deletions
diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
new file mode 100644
index 000000000..5e2a96a53
--- /dev/null
+++ b/usrp2/control_lib/Makefile.srcs
@@ -0,0 +1,44 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Control Lib Sources
+##################################################
+CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../control_lib/, \
+CRC16_D16.v \
+atr_controller.v \
+bin2gray.v \
+dcache.v \
+decoder_3_8.v \
+dpram32.v \
+gray2bin.v \
+gray_send.v \
+icache.v \
+mux4.v \
+mux8.v \
+nsgpio.v \
+ram_2port.v \
+ram_harv_cache.v \
+ram_loader.v \
+setting_reg.v \
+settings_bus.v \
+settings_bus_crossclock.v \
+srl.v \
+system_control.v \
+wb_1master.v \
+wb_readback_mux.v \
+simple_uart.v \
+simple_uart_tx.v \
+simple_uart_rx.v \
+oneshot_2clk.v \
+sd_spi.v \
+sd_spi_wb.v \
+wb_bridge_16_32.v \
+reset_sync.v \
+priority_enc.v \
+pic.v \
+longfifo.v \
+shortfifo.v \
+medfifo.v \
+))