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author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:46:58 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:46:58 -0800 |
commit | a170b9b42345794429486dd4f3316e84ea2cc871 (patch) | |
tree | 2483dfa9eb239e3c2cec5701da6f2f5b5940d7ad /usrp1/sdr_lib/ram64.v | |
parent | 320c70016f8798cb73c8d02eaa3728df48b5b3ab (diff) | |
download | uhd-a170b9b42345794429486dd4f3316e84ea2cc871.tar.gz uhd-a170b9b42345794429486dd4f3316e84ea2cc871.tar.bz2 uhd-a170b9b42345794429486dd4f3316e84ea2cc871.zip |
Moved usrp1 fpga files into usrp1 subdir.
Diffstat (limited to 'usrp1/sdr_lib/ram64.v')
-rw-r--r-- | usrp1/sdr_lib/ram64.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/usrp1/sdr_lib/ram64.v b/usrp1/sdr_lib/ram64.v new file mode 100644 index 000000000..084545808 --- /dev/null +++ b/usrp1/sdr_lib/ram64.v @@ -0,0 +1,16 @@ + + +module ram64 (input clock, input write, + input [5:0] wr_addr, input [15:0] wr_data, + input [5:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:63]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram64 |