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author | Matt Ettus <matt@ettus.com> | 2010-03-25 17:35:05 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-03-25 17:35:05 -0700 |
commit | 16818dc98e97b69a028c47e66ebfb16e32565533 (patch) | |
tree | 011ff2bcc793d8b38d0fe34adc1bccceb6ab81b8 /usrp1/sdr_lib/ram64.v | |
parent | fdb6175aef0aa1896c6319d5425955ce0a5dc86b (diff) | |
parent | 904b35c689d38694913606c569a9d324533ff765 (diff) | |
download | uhd-16818dc98e97b69a028c47e66ebfb16e32565533.tar.gz uhd-16818dc98e97b69a028c47e66ebfb16e32565533.tar.bz2 uhd-16818dc98e97b69a028c47e66ebfb16e32565533.zip |
Merge branch 'master' into udp
Diffstat (limited to 'usrp1/sdr_lib/ram64.v')
-rw-r--r-- | usrp1/sdr_lib/ram64.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/usrp1/sdr_lib/ram64.v b/usrp1/sdr_lib/ram64.v new file mode 100644 index 000000000..084545808 --- /dev/null +++ b/usrp1/sdr_lib/ram64.v @@ -0,0 +1,16 @@ + + +module ram64 (input clock, input write, + input [5:0] wr_addr, input [15:0] wr_data, + input [5:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:63]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram64 |