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authorJosh Blum <josh@joshknows.com>2010-01-22 11:58:32 -0800
committerJosh Blum <josh@joshknows.com>2010-01-22 11:58:32 -0800
commitda57b53f803af2598a06fa89e6da2797e5e65155 (patch)
treebfc0772d0cb7d880d1f91ed936baa02d8ac8d155 /usrp1/sdr_lib/hb/ram32_2sum.v
parent7bf8a6df381a667134b55701993c6770d32bc76b (diff)
parenta170b9b42345794429486dd4f3316e84ea2cc871 (diff)
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Merge branch 'usrp1' into usrp2
Conflicts: .gitignore
Diffstat (limited to 'usrp1/sdr_lib/hb/ram32_2sum.v')
-rw-r--r--usrp1/sdr_lib/hb/ram32_2sum.v22
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diff --git a/usrp1/sdr_lib/hb/ram32_2sum.v b/usrp1/sdr_lib/hb/ram32_2sum.v
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+
+
+module ram32_2sum (input clock, input write,
+ input [4:0] wr_addr, input [15:0] wr_data,
+ input [4:0] rd_addr1, input [4:0] rd_addr2,
+ output reg [15:0] sum);
+
+ reg [15:0] ram_array [0:31];
+ wire [16:0] sum_int;
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+ assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
+
+ always @(posedge clock)
+ sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
+
+
+endmodule // ram32_2sum
+