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| author | Matt Ettus <matt@ettus.com> | 2010-03-25 17:35:05 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-25 17:35:05 -0700 |
| commit | 16818dc98e97b69a028c47e66ebfb16e32565533 (patch) | |
| tree | 011ff2bcc793d8b38d0fe34adc1bccceb6ab81b8 /usrp1/sdr_lib/hb/acc.v | |
| parent | fdb6175aef0aa1896c6319d5425955ce0a5dc86b (diff) | |
| parent | 904b35c689d38694913606c569a9d324533ff765 (diff) | |
| download | uhd-16818dc98e97b69a028c47e66ebfb16e32565533.tar.gz uhd-16818dc98e97b69a028c47e66ebfb16e32565533.tar.bz2 uhd-16818dc98e97b69a028c47e66ebfb16e32565533.zip | |
Merge branch 'master' into udp
Diffstat (limited to 'usrp1/sdr_lib/hb/acc.v')
| -rw-r--r-- | usrp1/sdr_lib/hb/acc.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/usrp1/sdr_lib/hb/acc.v b/usrp1/sdr_lib/hb/acc.v new file mode 100644 index 000000000..195d5ea94 --- /dev/null +++ b/usrp1/sdr_lib/hb/acc.v @@ -0,0 +1,22 @@ + + +module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, + input signed [30:0] addend, output reg signed [33:0] sum ); + + always @(posedge clock) + if(reset) + sum <= #1 34'd0; + //else if(clear & enable_in) + // sum <= #1 addend; + //else if(clear) + // sum <= #1 34'd0; + else if(clear) + sum <= #1 addend; + else if(enable_in) + sum <= #1 sum + addend; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // acc + |