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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:58:32 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:58:32 -0800 |
| commit | da57b53f803af2598a06fa89e6da2797e5e65155 (patch) | |
| tree | bfc0772d0cb7d880d1f91ed936baa02d8ac8d155 /usrp1/sdr_lib/hb/acc.v | |
| parent | 7bf8a6df381a667134b55701993c6770d32bc76b (diff) | |
| parent | a170b9b42345794429486dd4f3316e84ea2cc871 (diff) | |
| download | uhd-da57b53f803af2598a06fa89e6da2797e5e65155.tar.gz uhd-da57b53f803af2598a06fa89e6da2797e5e65155.tar.bz2 uhd-da57b53f803af2598a06fa89e6da2797e5e65155.zip | |
Merge branch 'usrp1' into usrp2
Conflicts:
.gitignore
Diffstat (limited to 'usrp1/sdr_lib/hb/acc.v')
| -rw-r--r-- | usrp1/sdr_lib/hb/acc.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/usrp1/sdr_lib/hb/acc.v b/usrp1/sdr_lib/hb/acc.v new file mode 100644 index 000000000..195d5ea94 --- /dev/null +++ b/usrp1/sdr_lib/hb/acc.v @@ -0,0 +1,22 @@ + + +module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, + input signed [30:0] addend, output reg signed [33:0] sum ); + + always @(posedge clock) + if(reset) + sum <= #1 34'd0; + //else if(clear & enable_in) + // sum <= #1 addend; + //else if(clear) + // sum <= #1 34'd0; + else if(clear) + sum <= #1 addend; + else if(enable_in) + sum <= #1 sum + addend; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // acc + |