Moved usrp1 fpga files into usrp1 subdir.

1 files changed, 22 insertions, 0 deletions

diff --git a/usrp1/sdr_lib/hb/acc.v b/usrp1/sdr_lib/hb/acc.v
new file mode 100644
index 000000000..195d5ea94
--- /dev/null
+++ b/usrp1/sdr_lib/hb/acc.v
@@ -0,0 +1,22 @@
+
+
+module acc (input clock, input reset, input clear, input enable_in, output reg enable_out,
+	    input signed [30:0] addend, output reg signed [33:0] sum );
+
+   always @(posedge clock)
+     if(reset)
+       sum <= #1 34'd0;
+     //else if(clear & enable_in)
+     //  sum <= #1 addend;
+     //else if(clear)
+     //  sum <= #1 34'd0;
+     else if(clear)
+       sum <= #1 addend;
+     else if(enable_in)
+       sum <= #1 sum + addend;
+
+   always @(posedge clock)
+     enable_out <= #1 enable_in;
+   
+endmodule // acc
+