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author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:58:32 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:58:32 -0800 |
commit | da57b53f803af2598a06fa89e6da2797e5e65155 (patch) | |
tree | bfc0772d0cb7d880d1f91ed936baa02d8ac8d155 /usrp1/sdr_lib/dpram.v | |
parent | 7bf8a6df381a667134b55701993c6770d32bc76b (diff) | |
parent | a170b9b42345794429486dd4f3316e84ea2cc871 (diff) | |
download | uhd-da57b53f803af2598a06fa89e6da2797e5e65155.tar.gz uhd-da57b53f803af2598a06fa89e6da2797e5e65155.tar.bz2 uhd-da57b53f803af2598a06fa89e6da2797e5e65155.zip |
Merge branch 'usrp1' into usrp2
Conflicts:
.gitignore
Diffstat (limited to 'usrp1/sdr_lib/dpram.v')
-rw-r--r-- | usrp1/sdr_lib/dpram.v | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/usrp1/sdr_lib/dpram.v b/usrp1/sdr_lib/dpram.v new file mode 100644 index 000000000..28af90163 --- /dev/null +++ b/usrp1/sdr_lib/dpram.v @@ -0,0 +1,47 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + + +module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr); + parameter depth = 4; + parameter width = 16; + parameter size = 16; + + input wclk; + input [width-1:0] wdata; + input [depth-1:0] waddr; + input wen; + + input rclk; + output reg [width-1:0] rdata; + input [depth-1:0] raddr; + + reg [width-1:0] ram [0:size-1]; + + always @(posedge wclk) + if(wen) + ram[waddr] <= #1 wdata; + + always @(posedge rclk) + rdata <= #1 ram[raddr]; + +endmodule // dpram |