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authorJosh Blum <josh@joshknows.com>2010-01-22 11:58:32 -0800
committerJosh Blum <josh@joshknows.com>2010-01-22 11:58:32 -0800
commitda57b53f803af2598a06fa89e6da2797e5e65155 (patch)
treebfc0772d0cb7d880d1f91ed936baa02d8ac8d155 /usrp1/models/pll.v
parent7bf8a6df381a667134b55701993c6770d32bc76b (diff)
parenta170b9b42345794429486dd4f3316e84ea2cc871 (diff)
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Merge branch 'usrp1' into usrp2
Conflicts: .gitignore
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+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+// Very simple model for the PLL in the RX buffer
+
+module pll (inclk0,c0);
+
+ input inclk0;
+ output c0;
+
+ assign c0 = #9 inclk0;
+
+endmodule // pll
+
+