Moved usrp1 fpga files into usrp1 subdir.

1 files changed, 24 insertions, 0 deletions

diff --git a/usrp1/models/fifo_1k.v b/usrp1/models/fifo_1k.v
new file mode 100644
index 000000000..acfa4d176
--- /dev/null
+++ b/usrp1/models/fifo_1k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_1k
+  (  input [15:0] data,
+     input 	wrreq,
+     input 	rdreq,
+     input 	rdclk,
+     input 	wrclk,
+     input 	aclr,
+     output [15:0] q,
+     output 	 rdfull,
+     output 	 rdempty,
+     output [9:0] rdusedw,
+     output 	 wrfull,
+     output 	 wrempty,
+     output [9:0]  wrusedw
+     );
+
+fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_1k
+