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| author | Matt Ettus <matt@ettus.com> | 2011-05-23 18:21:09 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-07 14:42:58 -0700 |
| commit | 9451cb630962216492496f2f13d43ab2d08bde5d (patch) | |
| tree | ddc346598a175481bff70fa9d8462c855c3ce872 /usrp1/models/fifo.v | |
| parent | 58fe69310016580481d739cd3638633c446b5747 (diff) | |
| download | uhd-9451cb630962216492496f2f13d43ab2d08bde5d.tar.gz uhd-9451cb630962216492496f2f13d43ab2d08bde5d.tar.bz2 uhd-9451cb630962216492496f2f13d43ab2d08bde5d.zip | |
u2p: FPGA internal termination on the clock line from ADC
Diffstat (limited to 'usrp1/models/fifo.v')
0 files changed, 0 insertions, 0 deletions