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author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:58:32 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:58:32 -0800 |
commit | da57b53f803af2598a06fa89e6da2797e5e65155 (patch) | |
tree | bfc0772d0cb7d880d1f91ed936baa02d8ac8d155 /usrp1/models/bustri.v | |
parent | 7bf8a6df381a667134b55701993c6770d32bc76b (diff) | |
parent | a170b9b42345794429486dd4f3316e84ea2cc871 (diff) | |
download | uhd-da57b53f803af2598a06fa89e6da2797e5e65155.tar.gz uhd-da57b53f803af2598a06fa89e6da2797e5e65155.tar.bz2 uhd-da57b53f803af2598a06fa89e6da2797e5e65155.zip |
Merge branch 'usrp1' into usrp2
Conflicts:
.gitignore
Diffstat (limited to 'usrp1/models/bustri.v')
-rw-r--r-- | usrp1/models/bustri.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/usrp1/models/bustri.v b/usrp1/models/bustri.v new file mode 100644 index 000000000..6e5a0f74c --- /dev/null +++ b/usrp1/models/bustri.v @@ -0,0 +1,17 @@ + +// Model for tristate bus on altera +// FIXME do we really need to use a megacell for this? + +module bustri (data, + enabledt, + tridata); + + input [15:0] data; + input enabledt; + inout [15:0] tridata; + + assign tridata = enabledt ? data :16'bz; + +endmodule // bustri + + |