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author | Balint Seeber <balint@ettus.com> | 2013-11-19 18:41:27 -0800 |
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committer | Balint Seeber <balint@ettus.com> | 2013-11-19 18:41:27 -0800 |
commit | 58f4af976d64765c2402e1ce00ee78f4aae51881 (patch) | |
tree | ea3324800c51383b8e500188c2c3a43e0b34e21b /usrp1/megacells/sub32_bb.v | |
parent | f568b1984f77a525260b6a5157ce3a8f1ab56307 (diff) | |
download | uhd-58f4af976d64765c2402e1ce00ee78f4aae51881.tar.gz uhd-58f4af976d64765c2402e1ce00ee78f4aae51881.tar.bz2 uhd-58f4af976d64765c2402e1ce00ee78f4aae51881.zip |
b200: check return value from control write of FPGA bitstream for short transferrelease_003_006_000
Diffstat (limited to 'usrp1/megacells/sub32_bb.v')
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