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authorMatt Ettus <matt@ettus.com>2011-07-28 13:17:14 -0700
committerMatt Ettus <matt@ettus.com>2011-07-28 13:17:14 -0700
commit43087d47403bf93bf03b61b9c79472239c44808f (patch)
tree4fe7492d480b7e871e88b81ff6f0df2f31cd2626 /usrp1/megacells/sub32_bb.v
parent16f33c73b3a3303d183ebaabcb5fe968bb31c4e8 (diff)
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time: register time output to help fpga timing
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