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authorMatt Ettus <matt@ettus.com>2010-03-25 17:35:05 -0700
committerMatt Ettus <matt@ettus.com>2010-03-25 17:35:05 -0700
commit16818dc98e97b69a028c47e66ebfb16e32565533 (patch)
tree011ff2bcc793d8b38d0fe34adc1bccceb6ab81b8 /usrp1/megacells/pll_bb.v
parentfdb6175aef0aa1896c6319d5425955ce0a5dc86b (diff)
parent904b35c689d38694913606c569a9d324533ff765 (diff)
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+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module pll (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+endmodule
+