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| author | Matt Ettus <matt@ettus.com> | 2010-12-09 12:32:10 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-12-09 12:32:10 -0800 |
| commit | 0abb502d9e9aefc33ead200002906f70b7c982d5 (patch) | |
| tree | 434351c4d2c9ad9509912c9e47ff2c60469b41f7 /usrp1/megacells/dspclkpll.v | |
| parent | 355382f4c687f5d997f4589a34915d6e465bd387 (diff) | |
| parent | ac41c5a7adaf7f004c535b3a8b13aa5343562f50 (diff) | |
| download | uhd-0abb502d9e9aefc33ead200002906f70b7c982d5.tar.gz uhd-0abb502d9e9aefc33ead200002906f70b7c982d5.tar.bz2 uhd-0abb502d9e9aefc33ead200002906f70b7c982d5.zip | |
Merge branch 'time_compare_speedup' into ise12
* time_compare_speedup:
should safely delay the late signal which was causing timing problems
Diffstat (limited to 'usrp1/megacells/dspclkpll.v')
0 files changed, 0 insertions, 0 deletions