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author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:46:58 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:46:58 -0800 |
commit | a170b9b42345794429486dd4f3316e84ea2cc871 (patch) | |
tree | 2483dfa9eb239e3c2cec5701da6f2f5b5940d7ad /usrp1/megacells/addsub16_inst.v | |
parent | 320c70016f8798cb73c8d02eaa3728df48b5b3ab (diff) | |
download | uhd-a170b9b42345794429486dd4f3316e84ea2cc871.tar.gz uhd-a170b9b42345794429486dd4f3316e84ea2cc871.tar.bz2 uhd-a170b9b42345794429486dd4f3316e84ea2cc871.zip |
Moved usrp1 fpga files into usrp1 subdir.
Diffstat (limited to 'usrp1/megacells/addsub16_inst.v')
-rwxr-xr-x | usrp1/megacells/addsub16_inst.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/usrp1/megacells/addsub16_inst.v b/usrp1/megacells/addsub16_inst.v new file mode 100755 index 000000000..4a81ff2ee --- /dev/null +++ b/usrp1/megacells/addsub16_inst.v @@ -0,0 +1,9 @@ +addsub16 addsub16_inst ( + .add_sub ( add_sub_sig ), + .dataa ( dataa_sig ), + .datab ( datab_sig ), + .clock ( clock_sig ), + .aclr ( aclr_sig ), + .clken ( clken_sig ), + .result ( result_sig ) + ); |