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| author | Ian Buckley <ianb@server2.(none)> | 2010-09-01 03:08:11 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 12:10:34 -0800 |
| commit | 0a28cb5e7fbe81009e50fe03c4ffc3ce8db5052a (patch) | |
| tree | 866d3fdd06067d5aa68f1b0c1a0c4c8322c192f1 /usrp1/megacells/addsub16.inc | |
| parent | 0a272630e605b1ba71c0b7c8de9011c047cc578c (diff) | |
| download | uhd-0a28cb5e7fbe81009e50fe03c4ffc3ce8db5052a.tar.gz uhd-0a28cb5e7fbe81009e50fe03c4ffc3ce8db5052a.tar.bz2 uhd-0a28cb5e7fbe81009e50fe03c4ffc3ce8db5052a.zip | |
Added to DCM's and some BUFG's to align the internal 125MHz clock edge with its presentation externally at the NoBL SRAM.
Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA.
This hasn't been verified as working on a USRP2 yet.
Diffstat (limited to 'usrp1/megacells/addsub16.inc')
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