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authorJosh Blum <josh@joshknows.com>2010-01-22 11:46:58 -0800
committerJosh Blum <josh@joshknows.com>2010-01-22 11:46:58 -0800
commita170b9b42345794429486dd4f3316e84ea2cc871 (patch)
tree2483dfa9eb239e3c2cec5701da6f2f5b5940d7ad /usrp1/TODO
parent320c70016f8798cb73c8d02eaa3728df48b5b3ab (diff)
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Moved usrp1 fpga files into usrp1 subdir.
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+
+
+Area Reduction
+==============
+Reduce one or both stages of dec/interp to max rate of 8 instead of 16
+Optimize CICs to minimize registers
+Reduce width of RX CORDIC
+Fix CORDIC wasted logic cells from bad synthesis
+Progressively narrow x,y,z on CORDIC
+16-bit wide FIFOs, split IQ/channels on other side (?)
+
+Enhancements
+============
+Halfband filter in Spartan 3
+Muxing of inputs
+Switch over to newfc
+RAM interface?
+
+Other
+=====
+Capture/Transmit straight samples (no DUC/DDC)
+
+