Merged features/inband -r4812:5218 into trunk. This group of changes includes:

 * working stand-alone mblock code
 * work-in-progress on usrp inband signaling

usrp now depends on mblock, and guile is a dependency.



git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5221 221aa14e-8319-0410-a670-987f0aec2ac5

2 files changed, 25 insertions, 3 deletions

diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
index 2646d831f..8296a453e 100644
--- a/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
+++ b/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
@@ -27,7 +27,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 6.1
+set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1"
 
 # Pin & Location Assignments
 # ==========================
@@ -371,6 +371,13 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
 
 set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
+set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_fifo.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
 set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
@@ -405,5 +412,4 @@ set_global_assignment -name VERILOG_FILE usrp_inband_usb.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file
diff --git a/toplevel/usrp_inband_usb/usrp_inband_usb.v b/toplevel/usrp_inband_usb/usrp_inband_usb.v
index 55701b897..cc7490c5a 100644
--- a/toplevel/usrp_inband_usb/usrp_inband_usb.v
+++ b/toplevel/usrp_inband_usb/usrp_inband_usb.v
@@ -19,6 +19,7 @@
 //  along with this program; if not, write to the Free Software
 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
 //
+`define IN_BAND
 
 `include "config.vh"
 `include "../../../firmware/include/fpga_regs_common.v"
@@ -122,6 +123,20 @@ module usrp_inband_usb
    assign      bb_tx_i1 = ch2tx;
    assign      bb_tx_q1 = ch3tx;
    
+`ifdef IN_BAND
+ 	tx_buffer_inband tx_buffer
+     ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
+       .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
+       .channels({tx_numchan,1'b0}),
+       .tx_i_0(ch0tx),.tx_q_0(ch1tx),
+       .tx_i_1(ch2tx),.tx_q_1(ch3tx),
+       .tx_i_2(),.tx_q_2(),
+       .tx_i_3(),.tx_q_3(),
+       .txclk(clk64),.txstrobe(strobe_interp),
+       .clear_status(clear_status),
+       .tx_empty(tx_empty),
+       .debugbus(tx_debugbus) );
+`else
    tx_buffer tx_buffer
      ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
        .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
@@ -134,6 +149,7 @@ module usrp_inband_usb
        .clear_status(clear_status),
        .tx_empty(tx_empty),
        .debugbus(tx_debugbus) );
+`endif
 
  `ifdef TX_EN_0
    tx_chain tx_chain_0