diff options
| author | Matt Ettus <matt@ettus.com> | 2009-12-14 19:54:45 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-14 19:54:45 -0800 |
| commit | c64129bf5dcd9970fd6f70254ef3b93b662ca12f (patch) | |
| tree | 89bf9bd7d5f5ca6febcc41e92804fd3775581041 /top | |
| parent | 251b01d424da9612ef827fa5f13d61515d09a354 (diff) | |
| download | uhd-c64129bf5dcd9970fd6f70254ef3b93b662ca12f.tar.gz uhd-c64129bf5dcd9970fd6f70254ef3b93b662ca12f.tar.bz2 uhd-c64129bf5dcd9970fd6f70254ef3b93b662ca12f.zip | |
dsp_core_tx now has setting reg base settable from u2_core. underrun bug in vrt fixed
Diffstat (limited to 'top')
| -rw-r--r-- | top/u2_core/u2_core.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 8551efca0..f9ac07a55 100644 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -618,7 +618,7 @@ module u2_core assign debug_vt = debug_vtc | debug_vtd; - dsp_core_tx dsp_core_tx + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), @@ -729,8 +729,8 @@ module u2_core */ assign debug = debug_vt; - assign debug_gpio_0 = tx_data; - assign debug_gpio_1 = sample_tx; + assign debug_gpio_0 = sample_tx; + assign debug_gpio_1 = 32'hDEAD_BEEF; endmodule // u2_core |