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authorMatt Ettus <matt@ettus.com>2009-11-05 16:05:32 -0800
committerMatt Ettus <matt@ettus.com>2009-11-05 16:05:32 -0800
commita14a987ea5781d457aac1d7aca6937b27aaa53e0 (patch)
tree877330f86c62b1d7d02a5bc5a56e2987e90e1d14 /top
parent75f85f71aa34e5cd08feb983a2ff98f5a24bc1d2 (diff)
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vita rx instead of rx_control. Ready for firmware testing. Misses timing by a little bit, will worry later.
Diffstat (limited to 'top')
-rw-r--r--top/u2_core/u2_core.v24
-rw-r--r--top/u2_rev3/Makefile3
2 files changed, 25 insertions, 2 deletions
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index 5b272c366..48440e25c 100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -136,6 +136,7 @@ module u2_core
input [3:0] clock_divider
);
+ localparam SR_RXCTRL = 160;
localparam SR_TIME64 = 192;
wire [7:0] set_addr;
@@ -554,6 +555,7 @@ module u2_core
wire [31:0] sample_rx, sample_tx;
wire strobe_rx, strobe_tx;
+ /*
rx_control #(.FIFOSIZE(10)) rx_control
(.clk(dsp_clk), .rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -562,8 +564,26 @@ module u2_core
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
.fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
.debug_rx(debug_rx) );
-
- // dumkmy_rx dsp_core_rx
+*/
+ vita_rx_control #(.BASE(SR_RXCTRL)) vita_rx_control
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .vita_time(vita_time), .overrun(overrun),
+ .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+ .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy));
+
+ vita_rx_framer #(.BASE(SR_RXCTRL)) vita_rx_framer
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
+ .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
+ .fifo_occupied(), .fifo_full(), .fifo_empty() );
+
+ fifo_cascade #(.WIDTH(36), .SIZE(10)) rx_fifo_cascade
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
+ .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
+
dsp_core_rx dsp_core_rx
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
index 8b18550d1..a6fcc36f0 100644
--- a/top/u2_rev3/Makefile
+++ b/top/u2_rev3/Makefile
@@ -84,6 +84,8 @@ control_lib/wb_bridge_16_32.v \
control_lib/reset_sync.v \
control_lib/priority_enc.v \
control_lib/pic.v \
+vrt/vita_rx_control.v \
+vrt/vita_rx_framer.v \
simple_gemac/simple_gemac_wrapper.v \
simple_gemac/simple_gemac.v \
simple_gemac/simple_gemac_wb.v \
@@ -172,6 +174,7 @@ serdes/serdes_fc_tx.v \
serdes/serdes_rx.v \
serdes/serdes_tx.v \
timing/time_64bit.v \
+timing/time_compare.v \
timing/time_receiver.v \
timing/time_sender.v \
timing/time_sync.v \