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authorMatt Ettus <matt@ettus.com>2009-11-05 13:41:20 -0800
committerMatt Ettus <matt@ettus.com>2009-11-05 13:41:20 -0800
commit75f85f71aa34e5cd08feb983a2ff98f5a24bc1d2 (patch)
treea3e5960483c8314edad7c9cd05c6bc44c5279e21 /top
parent913cc668761c15d0f57caace2cd4df5b1a892063 (diff)
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put 64 bit timer for vita49 on the settings bus
Diffstat (limited to 'top')
-rw-r--r--[-rwxr-xr-x]top/u2_core/u2_core.v12
-rw-r--r--top/u2_rev3/Makefile1
2 files changed, 12 insertions, 1 deletions
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index fd17a10a7..5b272c366 100755..100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -135,6 +135,8 @@ module u2_core
input sim_mode,
input [3:0] clock_divider
);
+
+ localparam SR_TIME64 = 192;
wire [7:0] set_addr;
wire [31:0] set_data;
@@ -159,6 +161,7 @@ module u2_core
wire serdes_link_up;
wire epoch;
wire [31:0] irq;
+ wire [63:0] vita_time;
// ///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
@@ -560,7 +563,7 @@ module u2_core
.fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
.debug_rx(debug_rx) );
- // dummy_rx dsp_core_rx
+ // dumkmy_rx dsp_core_rx
dsp_core_rx dsp_core_rx
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -631,6 +634,13 @@ module u2_core
assign RAM_CE1n = 0;
assign RAM_D[17:16] = 2'bzz;
+ // /////////////////////////////////////////////////////////////////////////
+ // VITA Timing
+
+ time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+ (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .pps(pps_o), .vita_time(vita_time));
+
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
index 4358d7c56..8b18550d1 100644
--- a/top/u2_rev3/Makefile
+++ b/top/u2_rev3/Makefile
@@ -171,6 +171,7 @@ serdes/serdes_fc_rx.v \
serdes/serdes_fc_tx.v \
serdes/serdes_rx.v \
serdes/serdes_tx.v \
+timing/time_64bit.v \
timing/time_receiver.v \
timing/time_sender.v \
timing/time_sync.v \