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author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2009-04-22 00:11:28 +0000 |
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committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2009-04-22 00:11:28 +0000 |
commit | 0d440394746183c2ed2f39c7665cbf7b67a1764a (patch) | |
tree | c19c079c522a78a49034a3eb833146bff7542f99 /top/u2_rev3_iad/impulse.v | |
parent | 8c3ec58ceb58e8356557748de5d8f1077b4fef5f (diff) | |
download | uhd-0d440394746183c2ed2f39c7665cbf7b67a1764a.tar.gz uhd-0d440394746183c2ed2f39c7665cbf7b67a1764a.tar.bz2 uhd-0d440394746183c2ed2f39c7665cbf7b67a1764a.zip |
Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 FPGA build to use integrate-and-dump decimator instead of CIC/HB combination. This provides a much shorter time duration impulse response for the same decimation rate, at the expense of worse stop-band rejection.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10888 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'top/u2_rev3_iad/impulse.v')
-rw-r--r-- | top/u2_rev3_iad/impulse.v | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/top/u2_rev3_iad/impulse.v b/top/u2_rev3_iad/impulse.v new file mode 100644 index 000000000..ecdf101ab --- /dev/null +++ b/top/u2_rev3_iad/impulse.v @@ -0,0 +1,63 @@ +module impulse + (input clk, + input rst, + input ena, + + input [13:0] dc_offset_a, + input [13:0] dc_offset_b, + input [13:0] amplitude, + input [15:0] impulse_len, + input [15:0] zero_len, + + output [13:0] adc_a, + output [13:0] adc_b, + output adc_ovf_a, + output adc_ovf_b + ); + + reg [13:0] adc_a_int = 0; + reg [15:0] count; + + localparam ST_ZERO = 0; + localparam ST_HIGH = 1; + reg state; + + always @(posedge clk) + if (rst | ~ena) + begin + adc_a_int <= 0; + count <= 0; + state <= ST_ZERO; + end + else + case(state) + ST_ZERO: + if (count == zero_len) + begin + adc_a_int <= amplitude; + state <= ST_HIGH; + count <= 0; + end + else + count <= count + 1; + + ST_HIGH: + if (count == impulse_len) + begin + adc_a_int <= 0; + state <= ST_ZERO; + count <= 0; + end + else + count <= count + 1; + + endcase // case (state) + + assign adc_a = adc_a_int + dc_offset_a; + + // Ignore for now + assign adc_b = dc_offset_b; + assign adc_ovf_a = 0; + assign adc_ovf_b = 0; + +endmodule // adc_model |