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| author | Andrew Moch <Andrew.Moch@ni.com> | 2020-07-29 19:26:40 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-07-31 13:32:59 -0500 |
| commit | a68e7101167a4b5bf7b60ed90d963982aae735b8 (patch) | |
| tree | a5180460f4cc746467a00ceaf27fae72b1effc71 /tools | |
| parent | 473b0f5abe882ca316a7fe1a59234676940ef26b (diff) | |
| download | uhd-a68e7101167a4b5bf7b60ed90d963982aae735b8.tar.gz uhd-a68e7101167a4b5bf7b60ed90d963982aae735b8.tar.bz2 uhd-a68e7101167a4b5bf7b60ed90d963982aae735b8.zip | |
fpga: lib: Add xge features for new xport_sv
- Made some things optional to reduce logic when
used with the new xport_sv:
(1) Clocking to sys_clk
(2) Preamble insertion
- New options to CUTTHROUGH faster on the TX path.
The new xport_sv already has a gate to accumulate at
its clock crossing.
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions