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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-10-08 09:52:12 -0700 |
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| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-10-09 18:06:08 -0700 |
| commit | d655137c93c7622f86c0794efcf0044b009b1fb4 (patch) | |
| tree | dc0c2592bb7cf74c2138fdaceb76d3e69f25353e /tools/zpu-dissector/make-dissector-reg.py | |
| parent | d61baf0aea29645d75fc2bf6484f84530e0033a5 (diff) | |
| download | uhd-d655137c93c7622f86c0794efcf0044b009b1fb4.tar.gz uhd-d655137c93c7622f86c0794efcf0044b009b1fb4.tar.bz2 uhd-d655137c93c7622f86c0794efcf0044b009b1fb4.zip | |
x300: Reduced the TX buffer from 576K to 520K
- Trading performance for stability. This helps meet timing at the cost of a shorter processing time window between sends.
- Bumped FPGA compat number to 8
Diffstat (limited to 'tools/zpu-dissector/make-dissector-reg.py')
0 files changed, 0 insertions, 0 deletions