summaryrefslogtreecommitdiffstats
path: root/timing
diff options
context:
space:
mode:
authorMatt Ettus <matt@ettus.com>2010-01-18 17:56:55 -0800
committerMatt Ettus <matt@ettus.com>2010-01-18 17:56:55 -0800
commit89045982438e2fee8bd56b28a55c7b1c9a013a04 (patch)
treecd8d906df74ff8d47db9baed0bfa5abb6f18849e /timing
parent7ebcf79e38fabfbf689f1acc43052e635c6ad08d (diff)
downloaduhd-89045982438e2fee8bd56b28a55c7b1c9a013a04.tar.gz
uhd-89045982438e2fee8bd56b28a55c7b1c9a013a04.tar.bz2
uhd-89045982438e2fee8bd56b28a55c7b1c9a013a04.zip
remove time_sync and master_timer.
Master timer replaced with simple_timer which needs new memory map and control functions. it allows onetime and periodic interrupts. Copied from quad_radio time_sync functionality will go in time_64bit. Right now it only does external SMA connector, not mimo connector
Diffstat (limited to 'timing')
-rw-r--r--timing/simple_timer.v60
1 files changed, 60 insertions, 0 deletions
diff --git a/timing/simple_timer.v b/timing/simple_timer.v
new file mode 100644
index 000000000..17c7f1c36
--- /dev/null
+++ b/timing/simple_timer.v
@@ -0,0 +1,60 @@
+
+
+module simple_timer
+ #(parameter BASE=0)
+ (input clk, input reset,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ output reg onetime_int, output reg periodic_int);
+
+ reg [31:0] onetime_ctr;
+ always @(posedge clk)
+ if(reset)
+ begin
+ onetime_int <= 0;
+ onetime_ctr <= 0;
+ end
+ else
+ if(set_stb & (set_addr == BASE))
+ begin
+ onetime_int <= 0;
+ onetime_ctr <= set_data;
+ end
+ else
+ begin
+ if(onetime_ctr == 1)
+ onetime_int <= 1;
+ if(onetime_ctr != 0)
+ onetime_ctr <= onetime_ctr - 1;
+ else
+ onetime_int <= 0;
+ end // else: !if(set_stb & (set_addr == BASE))
+
+ reg [31:0] periodic_ctr, period;
+ always @(posedge clk)
+ if(reset)
+ begin
+ periodic_int <= 0;
+ periodic_ctr <= 0;
+ period <= 0;
+ end
+ else
+ if(set_stb & (set_addr == (BASE+1)))
+ begin
+ periodic_int <= 0;
+ periodic_ctr <= set_data;
+ period <= set_data;
+ end
+ else
+ if(periodic_ctr == 1)
+ begin
+ periodic_int <= 1;
+ periodic_ctr <= period;
+ end
+ else
+ if(periodic_ctr != 0)
+ begin
+ periodic_int <= 0;
+ periodic_ctr <= periodic_ctr - 1;
+ end
+
+endmodule // simple_timer