moved into subdir

8 files changed, 0 insertions, 551 deletions

diff --git a/timing/.gitignore b/timing/.gitignore
deleted file mode 100644
index 515552fdb..000000000
--- a/timing/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-/a.out
-/*.vcd
diff --git a/timing/time_64bit.v b/timing/time_64bit.v
deleted file mode 100644
index 84f79645c..000000000
--- a/timing/time_64bit.v
+++ /dev/null
@@ -1,86 +0,0 @@
-
-
-module time_64bit
-  #(parameter TICKS_PER_SEC = 32'd100000000,
-    parameter BASE = 0)
-    (input clk, input rst,
-     input set_stb, input [7:0] set_addr, input [31:0] set_data,  
-     input pps,
-     output [63:0] vita_time, output pps_int
-     );
-
-   localparam 	   NEXT_SECS = 0;   
-   localparam 	   NEXT_TICKS = 1;
-   localparam      PPS_POL = 2;
-   
-   localparam 	   ROLLOVER = TICKS_PER_SEC - 1;	   
-   
-   reg [31:0] 	   seconds;
-   reg [31:0] 	   ticks;
-   wire 	   end_of_second;
-   assign 	   vita_time = {seconds,ticks};
-   
-   wire [31:0] 	   next_ticks_preset;
-   wire [31:0] 	   next_seconds_preset;
-   wire 	   set_on_pps_trig;
-   reg 		   set_on_next_pps;
-   wire 	   pps_polarity;
-   
-   setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(next_ticks_preset),.changed());
-   
-   setting_reg #(.my_addr(BASE+NEXT_SECS)) sr_next_secs
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
-
-   setting_reg #(.my_addr(BASE+PPS_POL)) sr_pps_pol
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(pps_polarity),.changed());
-
-   reg [1:0] 	   pps_del;
-   reg 		   pps_reg_p, pps_reg_n, pps_reg;
-   wire 	   pps_edge;
-   
-   always @(posedge clk)  pps_reg_p <= pps;   
-   always @(negedge clk)  pps_reg_n <= pps;
-   always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
-   
-   always @(posedge clk)
-     if(rst)
-       pps_del <= 2'b00;
-     else
-       pps_del <= {pps_del[0],pps_reg};
-
-   assign pps_edge = pps_del[0] & ~pps_del[1];
-   
-   always @(posedge clk)
-     if(rst)
-       set_on_next_pps <= 0;
-     else if(set_on_pps_trig)
-       set_on_next_pps <= 1;
-     else if(pps_edge)
-       set_on_next_pps <= 0;
-   
-   always @(posedge clk)
-     if(rst)
-       begin
-	  seconds <= 32'd0;
-	  ticks <= 32'd0;
-       end
-     else if(pps_edge & set_on_next_pps)
-       begin
-	  seconds <= next_seconds_preset;
-	  ticks <= next_ticks_preset;
-       end
-     else if(ticks == ROLLOVER)
-       begin
-	  seconds <= seconds + 1;
-	  ticks <= 0;
-       end
-     else
-       ticks <= ticks + 1;
-
-   assign pps_int = pps_edge;
-   
-endmodule // time_64bit
diff --git a/timing/time_compare.v b/timing/time_compare.v
deleted file mode 100644
index a21c9f8e0..000000000
--- a/timing/time_compare.v
+++ /dev/null
@@ -1,23 +0,0 @@
-
-// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second
-
-module time_compare
-  (input [63:0] time_now,
-   input [63:0] trigger_time,
-   output now,
-   output early,
-   output late, 
-   output too_early);
-   
-   wire    sec_match   = (time_now[63:32] == trigger_time[63:32]);
-   wire    sec_late    = (time_now[63:32] > trigger_time[63:32]);
-
-   wire    tick_match  = (time_now[31:0] == trigger_time[31:0]);
-   wire    tick_late   = (time_now[31:0] > trigger_time[31:0]);
-   
-   assign now 	       = sec_match & tick_match;
-   assign late 	       = sec_late | (sec_match & tick_late);
-   assign early        = ~now & ~late;
-   assign too_early    = (trigger_time[63:32] > (time_now[63:32] + 4));  // Don't wait too long
-   
-endmodule // time_compare
diff --git a/timing/time_receiver.v b/timing/time_receiver.v
deleted file mode 100644
index 8e7d3f1ea..000000000
--- a/timing/time_receiver.v
+++ /dev/null
@@ -1,94 +0,0 @@
-
-module time_receiver
-  (input clk, input rst,
-   output [31:0] master_time,
-   output sync_rcvd,
-   input exp_pps_in);
-
-   wire       code_err, disp_err, dispout, complete_word;
-   reg 	      disp_reg;
-   reg [9:0]  shiftreg;
-   reg [3:0]  bit_count;
-   wire [8:0] dataout;
-   reg [8:0]  dataout_reg;
- 	      
-   always @(posedge clk)
-     shiftreg <= {exp_pps_in, shiftreg[9:1]};
-
-   localparam COMMA_0 = 10'h283;
-   localparam COMMA_1 = 10'h17c;
-   
-   wire       found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1);
-   wire       set_disp = (shiftreg == COMMA_1);
-
-   always @(posedge clk)
-     if(rst)
-       bit_count <= 0;
-     else if(found_comma | complete_word)
-       bit_count <= 0;
-     else 
-       bit_count <= bit_count + 1;
-   assign     complete_word = (bit_count == 9);
-
-   always @(posedge clk)
-     if(set_disp)
-       disp_reg <= 1;
-     else if(complete_word)
-       disp_reg <= dispout;
-
-   always @(posedge clk)
-     if(complete_word)
-       dataout_reg <= dataout;
-     
-   decode_8b10b decode_8b10b 
-     (.datain(shiftreg),.dispin(disp_reg),
-      .dataout(dataout),.dispout(dispout),
-      .code_err(code_err),.disp_err(disp_err) );
-
-   reg 	      error;
-   always @(posedge clk)
-     if(complete_word)
-       error <= code_err | disp_err;
-   
-   localparam STATE_IDLE = 0;
-   localparam STATE_T0 = 1;
-   localparam STATE_T1 = 2;
-   localparam STATE_T2 = 3;
-   localparam STATE_T3 = 4;
-   
-   localparam HEAD = 9'h13c;   
-
-   reg [7:0]  clock_a, clock_b, clock_c;
-   reg [2:0]  state;
-   
-   always @(posedge clk)
-     if(rst)
-       state <= STATE_IDLE;
-     else if(complete_word)
-       case(state)
-	 STATE_IDLE :
-	   if(dataout_reg == HEAD)
-	     state <= STATE_T0;
-	 STATE_T0 :
-	   begin
-	      clock_a <= dataout_reg[7:0];
-	      state <= STATE_T1;
-	   end
-	 STATE_T1 :
-	   begin
-	      clock_b <= dataout_reg[7:0];
-	      state <= STATE_T2;
-	   end
-	 STATE_T2 :
-	   begin
-	      clock_c <= dataout_reg[7:0];
-	      state <= STATE_T3;
-	   end
-	 STATE_T3 :
-	   state <= STATE_IDLE;
-       endcase // case(state)
-
-   assign master_time =  {clock_a, clock_b, clock_c, dataout_reg[7:0]};
-   assign sync_rcvd = (complete_word & (state == STATE_T3));
-
-endmodule // time_sender
diff --git a/timing/time_sender.v b/timing/time_sender.v
deleted file mode 100644
index aa2fcbbdb..000000000
--- a/timing/time_sender.v
+++ /dev/null
@@ -1,110 +0,0 @@
-
-
-module time_sender
-  (input clk, input rst,
-   input [31:0] master_time,
-   input send_sync,
-   output exp_pps_out);
-
-   reg [7:0] datain;
-   reg 	     k;
-   wire [9:0] dataout;
-   reg [9:0] dataout_reg;
-   reg 	     disp_reg;
-   wire      disp, new_word;
-   
-   encode_8b10b encode_8b10b 
-     (.datain({k,datain}),.dispin(disp_reg),
-      .dataout(dataout),.dispout(disp));
-
-   assign    exp_pps_out = dataout_reg[0];
-
-   always @(posedge clk)
-     if(rst)
-       disp_reg <= 0;
-     else if(new_word)
-       disp_reg <= disp;
-   
-   always @(posedge clk)
-     if(rst)
-       dataout_reg <= 0;
-     else if(new_word)
-       dataout_reg <= dataout;
-     else
-       dataout_reg <= {1'b0,dataout_reg[9:1]};
-   
-   reg [4:0] state;
-   reg [3:0] bit_count;
-
-   assign    new_word = (bit_count == 9);
-   
-   always @(posedge clk)
-     if(rst)
-       bit_count <= 0;
-     else if(new_word | send_sync)
-       bit_count <= 0;
-     else
-       bit_count <= bit_count + 1;
-
-   localparam SEND_IDLE = 0;
-   localparam SEND_HEAD = 1;
-   localparam SEND_T0 = 2;
-   localparam SEND_T1 = 3;
-   localparam SEND_T2 = 4;
-   localparam SEND_T3 = 5;
-
-   localparam COMMA = 8'hBC;
-   localparam HEAD = 8'h3C;
-
-   reg [31:0] master_time_reg;
-   
-   always @(posedge clk)
-     if(rst)
-       master_time_reg <= 0;
-     else if(send_sync)
-       master_time_reg <= master_time;
-   
-   always @(posedge clk)
-     if(rst)
-       begin
-	  {k,datain} <= 0;
-	  state <= SEND_IDLE;
-       end
-     else
-       if(send_sync)
-	 state <= SEND_HEAD;
-       else if(new_word)
-	 case(state)
-	   SEND_IDLE :
-	     {k,datain} <= {1'b1,COMMA};
-	   SEND_HEAD :
-	     begin
-		{k,datain} <= {1'b1, HEAD};
-		state <= SEND_T0;
-	     end
-	   SEND_T0 :
-	     begin
-		{k,datain} <= {1'b0, master_time_reg[31:24] };
-		state <= SEND_T1;
-	     end
-	   SEND_T1 :
-	     begin
-		{k,datain} <= {1'b0, master_time_reg[23:16]};
-		state <= SEND_T2;
-	     end
-	   SEND_T2 :
-	     begin
-		{k,datain} <= {1'b0, master_time_reg[15:8]};
-		state <= SEND_T3;
-	     end
-	   SEND_T3 :
-	     begin
-		{k,datain} <= {1'b0, master_time_reg[7:0]};
-		state <= SEND_IDLE;
-	     end
-	   default :
-	     state <= SEND_IDLE;
-	 endcase // case(state)
-   
-   
-endmodule // time_sender
diff --git a/timing/time_sync.v b/timing/time_sync.v
deleted file mode 100644
index c0c8e195f..000000000
--- a/timing/time_sync.v
+++ /dev/null
@@ -1,146 +0,0 @@
-
-
-module time_sync
-  (input wb_clk_i, input rst_i,
-   input cyc_i, input stb_i, input [2:0] adr_i,
-   input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
-   input sys_clk_i, output [31:0] master_time_o,
-   input pps_posedge, input pps_negedge, 
-   input exp_pps_in, output exp_pps_out,
-   output reg int_o,
-   output reg epoch_o,
-   output reg pps_o );
-   
-   wire [31:0] master_time_rcvd;
-   reg [31:0]  master_time;
-   reg [31:0]  delta_time;
-
-   reg 	       internal_tick;
-   wire        sync_rcvd, pps_ext;
-   reg [31:0]  tick_time, tick_time_wb;
-   wire        tick_free_run;
-   reg 	       tick_int_enable, tick_source, external_sync;
-   reg [31:0]  tick_interval;
-   reg 	       sync_on_next_pps;
-   reg         sync_every_pps;
-   reg 	       pps_edge;
-   
-   // Generate master time
-   always @(posedge sys_clk_i)
-     if(rst_i)
-       master_time <= 0;
-     else if(external_sync & sync_rcvd)
-       master_time <= master_time_rcvd + delta_time;
-     else if(pps_ext & (sync_on_next_pps|sync_every_pps))
-       master_time <= 0;
-     else
-       master_time <= master_time + 1;
-   assign      master_time_o = master_time;
-   
-   time_sender time_sender
-     (.clk(sys_clk_i),.rst(rst_i),
-      .master_time(master_time),
-      .send_sync(internal_tick),
-      .exp_pps_out(exp_pps_out) );
-
-   time_receiver time_receiver
-     (.clk(sys_clk_i),.rst(rst_i),
-      .master_time(master_time_rcvd),
-      .sync_rcvd(sync_rcvd),
-      .exp_pps_in(exp_pps_in) );
-
-   assign     ack_o = stb_i;
-   wire       wb_write = cyc_i & stb_i & we_i;
-   wire       wb_read = cyc_i & stb_i & ~we_i;
-   wire       wb_acc = cyc_i & stb_i;
-   
-   always @(posedge wb_clk_i)
-     if(rst_i)
-       begin
-	  tick_source <= 0;
-	  tick_int_enable <= 0;
-	  external_sync <= 0;
-	  tick_interval <= 100000-1;  // default to 1K times per second
-	  delta_time <= 0;
-	  pps_edge <= 0;
-	  sync_every_pps <= 0;
-       end
-     else if(wb_write)
-       case(adr_i[2:0])
-	 3'd0 :
-	   begin
-	      tick_source <= dat_i[0];
-	      tick_int_enable <= dat_i[1];
-	      external_sync <= dat_i[2];
-	      pps_edge <= dat_i[3];
-	      sync_every_pps <= dat_i[4];
-	   end
-	 3'd1 :
-	   tick_interval <= dat_i;
-	 3'd2 :
-	   delta_time <= dat_i;
-	 3'd3 :
-	   ;
-	 // Do nothing here, this is to arm the sync_on_next
-       endcase // case(adr_i[2:0])
-
-   always @(posedge sys_clk_i)
-     if(rst_i)
-       sync_on_next_pps <= 0;
-     else if(pps_ext)
-       sync_on_next_pps <= 0;
-     else if(wb_write & (adr_i[2:0] == 3))
-       sync_on_next_pps <= 1;
-   
-   always @(posedge sys_clk_i)
-     if(internal_tick)
-       tick_time <= master_time;
-
-   always @(posedge wb_clk_i)
-     tick_time_wb <= tick_time;
-   
-   assign dat_o = tick_time_wb;
-
-   always @(posedge sys_clk_i)
-     internal_tick <= (tick_source == 0) ? tick_free_run : pps_ext;
-
-   reg [31:0] counter;
-   always @(posedge sys_clk_i)
-     if(rst_i)
-       counter <= 0;
-     else if(tick_free_run)
-       counter <= 0;
-     else
-       counter <= counter + 1;
-   assign     tick_free_run = (counter >= tick_interval);
-   
-   // Properly Latch and edge detect External PPS input
-   reg 	      pps_in_d1, pps_in_d2;
-   always @(posedge sys_clk_i)
-     begin
-	pps_in_d1 <= pps_edge ? pps_posedge : pps_negedge;
-	pps_in_d2 <= pps_in_d1;
-     end
-   assign pps_ext = pps_in_d1 & ~pps_in_d2;
-
-   always @(posedge sys_clk_i)
-     pps_o <= pps_ext;
-   
-   // Need to register this?
-   reg 	  internal_tick_d1;
-   always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick;
-   
-   always @(posedge wb_clk_i)
-     if(rst_i)
-       int_o <= 0;
-     else if(tick_int_enable & (internal_tick | internal_tick_d1))
-       int_o <= 1;
-     else
-       int_o <= 0;
-
-   always @(posedge sys_clk_i)
-     if(rst_i)
-       epoch_o <= 0;
-     else
-       epoch_o <= (master_time_o[27:0] == 0);
-endmodule // time_sync
diff --git a/timing/time_transfer_tb.v b/timing/time_transfer_tb.v
deleted file mode 100644
index 2b75c60bd..000000000
--- a/timing/time_transfer_tb.v
+++ /dev/null
@@ -1,50 +0,0 @@
-
-`timescale 1ns / 1ps
-
-module time_transfer_tb();
-
-   reg clk = 0, rst = 1;
-   always #5 clk = ~clk;
-   
-   initial 
-     begin
-	@(negedge clk);
-	@(negedge clk);
-	rst <= 0;
-     end
-
-   initial $dumpfile("time_transfer_tb.vcd");
-   initial $dumpvars(0,time_transfer_tb);
-   
-   initial #100000000 $finish;
-
-   wire exp_pps, pps, pps_rcv;
-   wire [31:0] master_clock_rcv;
-   reg [31:0]  master_clock = 0;
-   reg [31:0]  counter = 0;
-
-   localparam  PPS_PERIOD = 109;
-   always @(posedge clk)
-     if(counter == PPS_PERIOD)
-       counter <= 0;
-     else
-       counter <= counter + 1;
-   assign      pps = (counter == (PPS_PERIOD-1));
-   
-   always @(posedge clk)
-     master_clock <= master_clock + 1;
-   
-   time_sender time_sender
-     (.clk(clk),.rst(rst),
-      .master_clock(master_clock),
-      .pps(pps),
-      .exp_pps_out(exp_pps) );
-
-   time_receiver time_receiver
-     (.clk(clk),.rst(rst),
-      .master_clock(master_clock_rcv),
-      .pps(pps_rcv),
-      .exp_pps_in(exp_pps) );
-
-   wire [31:0] delta = master_clock - master_clock_rcv;
-endmodule // time_transfer_tb
diff --git a/timing/timer.v b/timing/timer.v
deleted file mode 100644
index 70c9746be..000000000
--- a/timing/timer.v
+++ /dev/null
@@ -1,40 +0,0 @@
-
-
-module timer
-  (input wb_clk_i, input rst_i,
-   input cyc_i, input stb_i, input [2:0] adr_i,
-   input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
-   input sys_clk_i, input [31:0] master_time_i,
-   output int_o );
-
-   reg [31:0] time_wb;
-   always @(posedge wb_clk_i)
-     time_wb <= master_time_i;
-
-   assign     ack_o = stb_i;
-
-   reg [31:0] int_time;
-   reg 	      int_reg;
-   
-   always @(posedge sys_clk_i)
-     if(rst_i)
-       begin
-	  int_time <= 0;
-	  int_reg <= 0;
-       end
-     else if(|int_time && (master_time_i == int_time))
-       begin
-	  int_time <= 0;
-	  int_reg <= 1;
-       end
-     else if(stb_i & we_i)
-       begin
-	  int_time <= dat_i;
-	  int_reg <= 0;
-       end
-
-   assign dat_o = time_wb;
-   assign int_o = int_reg;
-   
-endmodule // timer
-