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author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
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committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /timing/time_receiver.v | |
download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'timing/time_receiver.v')
-rw-r--r-- | timing/time_receiver.v | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/timing/time_receiver.v b/timing/time_receiver.v new file mode 100644 index 000000000..8e7d3f1ea --- /dev/null +++ b/timing/time_receiver.v @@ -0,0 +1,94 @@ + +module time_receiver + (input clk, input rst, + output [31:0] master_time, + output sync_rcvd, + input exp_pps_in); + + wire code_err, disp_err, dispout, complete_word; + reg disp_reg; + reg [9:0] shiftreg; + reg [3:0] bit_count; + wire [8:0] dataout; + reg [8:0] dataout_reg; + + always @(posedge clk) + shiftreg <= {exp_pps_in, shiftreg[9:1]}; + + localparam COMMA_0 = 10'h283; + localparam COMMA_1 = 10'h17c; + + wire found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1); + wire set_disp = (shiftreg == COMMA_1); + + always @(posedge clk) + if(rst) + bit_count <= 0; + else if(found_comma | complete_word) + bit_count <= 0; + else + bit_count <= bit_count + 1; + assign complete_word = (bit_count == 9); + + always @(posedge clk) + if(set_disp) + disp_reg <= 1; + else if(complete_word) + disp_reg <= dispout; + + always @(posedge clk) + if(complete_word) + dataout_reg <= dataout; + + decode_8b10b decode_8b10b + (.datain(shiftreg),.dispin(disp_reg), + .dataout(dataout),.dispout(dispout), + .code_err(code_err),.disp_err(disp_err) ); + + reg error; + always @(posedge clk) + if(complete_word) + error <= code_err | disp_err; + + localparam STATE_IDLE = 0; + localparam STATE_T0 = 1; + localparam STATE_T1 = 2; + localparam STATE_T2 = 3; + localparam STATE_T3 = 4; + + localparam HEAD = 9'h13c; + + reg [7:0] clock_a, clock_b, clock_c; + reg [2:0] state; + + always @(posedge clk) + if(rst) + state <= STATE_IDLE; + else if(complete_word) + case(state) + STATE_IDLE : + if(dataout_reg == HEAD) + state <= STATE_T0; + STATE_T0 : + begin + clock_a <= dataout_reg[7:0]; + state <= STATE_T1; + end + STATE_T1 : + begin + clock_b <= dataout_reg[7:0]; + state <= STATE_T2; + end + STATE_T2 : + begin + clock_c <= dataout_reg[7:0]; + state <= STATE_T3; + end + STATE_T3 : + state <= STATE_IDLE; + endcase // case(state) + + assign master_time = {clock_a, clock_b, clock_c, dataout_reg[7:0]}; + assign sync_rcvd = (complete_word & (state == STATE_T3)); + +endmodule // time_sender |