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author | Matt Ettus <matt@ettus.com> | 2009-11-05 16:05:32 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2009-11-05 16:05:32 -0800 |
commit | a14a987ea5781d457aac1d7aca6937b27aaa53e0 (patch) | |
tree | 877330f86c62b1d7d02a5bc5a56e2987e90e1d14 /timing/time_compare.v | |
parent | 75f85f71aa34e5cd08feb983a2ff98f5a24bc1d2 (diff) | |
download | uhd-a14a987ea5781d457aac1d7aca6937b27aaa53e0.tar.gz uhd-a14a987ea5781d457aac1d7aca6937b27aaa53e0.tar.bz2 uhd-a14a987ea5781d457aac1d7aca6937b27aaa53e0.zip |
vita rx instead of rx_control. Ready for firmware testing. Misses timing by a little bit, will worry later.
Diffstat (limited to 'timing/time_compare.v')
-rw-r--r-- | timing/time_compare.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/timing/time_compare.v b/timing/time_compare.v new file mode 100644 index 000000000..edfa7375a --- /dev/null +++ b/timing/time_compare.v @@ -0,0 +1,21 @@ + +// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second + +module time_compare + (input [63:0] time_now, + input [63:0] trigger_time, + output now, + output early, + output late); + + wire sec_match = (time_now[63:32] == trigger_time[63:32]); + wire sec_late = (time_now[63:32] > trigger_time[63:32]); + + wire tick_match = (time_now[31:0] == trigger_time[31:0]); + wire tick_late = (time_now[31:0] > trigger_time[31:0]); + + assign now = sec_match & tick_match; + assign late = sec_late | (sec_match & tick_late); + assign early = ~now & ~late; + +endmodule // time_compare |