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author | Matt Ettus <matt@ettus.com> | 2010-01-25 13:24:53 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2010-01-25 13:24:53 -0800 |
commit | 058780d92f776bcba0a384b5e4c4aa948d64c6f4 (patch) | |
tree | 265ec9cbeb67bdbc0529b22209eb37f57008dc25 /timing/simple_timer.v | |
parent | a8ceedc34bb66c870964e4430c098a2cdaf9d429 (diff) | |
parent | 8d19387a8642caf74179bdcb7eddf1936f473e53 (diff) | |
download | uhd-058780d92f776bcba0a384b5e4c4aa948d64c6f4.tar.gz uhd-058780d92f776bcba0a384b5e4c4aa948d64c6f4.tar.bz2 uhd-058780d92f776bcba0a384b5e4c4aa948d64c6f4.zip |
Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp
Merge latest VRT changes into UDP branch. Merged from 1 behind the
head of VRT because the head moved things around and confused git
Conflicts:
usrp2/timing/time_64bit.v
usrp2/top/u2_core/u2_core.v
Diffstat (limited to 'timing/simple_timer.v')
-rw-r--r-- | timing/simple_timer.v | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/timing/simple_timer.v b/timing/simple_timer.v new file mode 100644 index 000000000..17c7f1c36 --- /dev/null +++ b/timing/simple_timer.v @@ -0,0 +1,60 @@ + + +module simple_timer + #(parameter BASE=0) + (input clk, input reset, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + output reg onetime_int, output reg periodic_int); + + reg [31:0] onetime_ctr; + always @(posedge clk) + if(reset) + begin + onetime_int <= 0; + onetime_ctr <= 0; + end + else + if(set_stb & (set_addr == BASE)) + begin + onetime_int <= 0; + onetime_ctr <= set_data; + end + else + begin + if(onetime_ctr == 1) + onetime_int <= 1; + if(onetime_ctr != 0) + onetime_ctr <= onetime_ctr - 1; + else + onetime_int <= 0; + end // else: !if(set_stb & (set_addr == BASE)) + + reg [31:0] periodic_ctr, period; + always @(posedge clk) + if(reset) + begin + periodic_int <= 0; + periodic_ctr <= 0; + period <= 0; + end + else + if(set_stb & (set_addr == (BASE+1))) + begin + periodic_int <= 0; + periodic_ctr <= set_data; + period <= set_data; + end + else + if(periodic_ctr == 1) + begin + periodic_int <= 1; + periodic_ctr <= period; + end + else + if(periodic_ctr != 0) + begin + periodic_int <= 0; + periodic_ctr <= periodic_ctr - 1; + end + +endmodule // simple_timer |