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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
| commit | 8b377a9d6d0ad281474a8dbff49ea3b093178b28 (patch) | |
| tree | 8e3c7a1b60f96df6e2140666d3b7afa5166d885d /testbench/cmdfile | |
| parent | e92d36dcfe02afaedec348f2d8fc4523fb4e633b (diff) | |
| download | uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.gz uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.bz2 uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.zip | |
moved into subdir
Diffstat (limited to 'testbench/cmdfile')
| -rw-r--r-- | testbench/cmdfile | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/testbench/cmdfile b/testbench/cmdfile deleted file mode 100644 index 8083eb92a..000000000 --- a/testbench/cmdfile +++ /dev/null @@ -1,27 +0,0 @@ - -# My stuff --y . --y ../top/u2_core --y ../control_lib --y ../control_lib/newfifo --y ../serdes --y ../sdr_lib --y ../timing --y ../coregen --y ../extram --y ../simple_gemac --y ../simple_gemac/miim - -# Models --y ../models --y ../models/CY7C1356C - -# Open Cores --y ../opencores/8b10b --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog --y ../opencores/aemb/rtl/verilog --y ../opencores/simple_pic/rtl - |