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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /testbench/cmdfile | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'testbench/cmdfile')
| -rw-r--r-- | testbench/cmdfile | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/testbench/cmdfile b/testbench/cmdfile deleted file mode 100644 index 8083eb92a..000000000 --- a/testbench/cmdfile +++ /dev/null @@ -1,27 +0,0 @@ - -# My stuff --y . --y ../top/u2_core --y ../control_lib --y ../control_lib/newfifo --y ../serdes --y ../sdr_lib --y ../timing --y ../coregen --y ../extram --y ../simple_gemac --y ../simple_gemac/miim - -# Models --y ../models --y ../models/CY7C1356C - -# Open Cores --y ../opencores/8b10b --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog --y ../opencores/aemb/rtl/verilog --y ../opencores/simple_pic/rtl - |