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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /testbench/U2_SIM.sav | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'testbench/U2_SIM.sav')
| -rw-r--r-- | testbench/U2_SIM.sav | 95 |
1 files changed, 0 insertions, 95 deletions
diff --git a/testbench/U2_SIM.sav b/testbench/U2_SIM.sav deleted file mode 100644 index d320c2b6c..000000000 --- a/testbench/U2_SIM.sav +++ /dev/null @@ -1,95 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -u2_sim_top.adc_oen_a -u2_sim_top.adc_oen_b -u2_sim_top.adc_pdn_a -u2_sim_top.adc_pdn_b -u2_sim_top.aux_clk -u2_sim_top.POR -u2_sim_top.clk_fpga -u2_sim_top.clk_en[1:0] -u2_sim_top.clk_sel[1:0] -u2_sim_top.led1 -u2_sim_top.led2 -u2_sim_top.sclk -u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0] -u2_sim_top.sda_pad_o -u2_sim_top.sda_pad_oen_o -u2_sim_top.sdi -u2_sim_top.sdo -u2_sim_top.sen_clk -u2_sim_top.sen_dac -u2_sim_top.ser_enable -u2_sim_top.ser_loopen -u2_sim_top.ser_prbsen -u2_sim_top.ser_rx_en -u2_sim_top.u2_basic.sysctrl.start -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.done -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.sysctrl.aux_clk -u2_sim_top.u2_basic.sysctrl.clk_fpga -u2_sim_top.u2_basic.sysctrl.done -u2_sim_top.u2_basic.bus_writer.start -u2_sim_top.u2_basic.bus_writer.done -@22 -u2_sim_top.u2_basic.bus_writer.rom_addr[15:0] -u2_sim_top.u2_basic.bus_writer.rom_data[47:0] -u2_sim_top.u2_basic.bus_writer.state[3:0] -@29 -u2_sim_top.u2_basic.bus_writer.wb_ack_i -@22 -u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0] -@28 -u2_sim_top.u2_basic.bus_writer.wb_clk_i -u2_sim_top.u2_basic.bus_writer.wb_cyc_o -@22 -u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0] -u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0] -@28 -u2_sim_top.u2_basic.bus_writer.wb_stb_o -u2_sim_top.u2_basic.bus_writer.wb_we_o -u2_sim_top.u2_basic.bus_writer.wb_rst_i -u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0] -u2_sim_top.sda_pad_i -u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i -u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o -@22 -u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0] -u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0] -@28 -u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i -u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i -u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i -u2_sim_top.u2_basic.control_lines.wb_cyc_i -u2_sim_top.u2_basic.control_lines.wb_stb_i -u2_sim_top.u2_basic.control_lines.wb_we_i -u2_sim_top.u2_basic.control_lines.wb_ack_o -u2_sim_top.u2_basic.s0_ack -@22 -u2_sim_top.u2_basic.control_lines.internal_reg[31:0] -u2_sim_top.u2_basic.control_lines.port_output[31:0] -@28 -u2_sim_top.u2_basic.led1 -u2_sim_top.u2_basic.led2 -@22 -u2_sim_top.u2_basic.misc_outs[7:0] -u2_sim_top.u2_basic.clock_outs[7:0] -u2_sim_top.u2_basic.adc_outs[7:0] -u2_sim_top.u2_basic.serdes_outs[7:0] -@28 -u2_sim_top.u2_basic.shared_spi.miso_pad_i -u2_sim_top.u2_basic.shared_spi.mosi_pad_o -@22 -u2_sim_top.u2_basic.shared_spi.ss[7:0] -u2_sim_top.u2_basic.shared_spi.divider[15:0] -@28 -u2_sim_top.u2_basic.shared_spi.sclk_pad_o -@22 -u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] |