diff options
| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
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| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /testbench/PAUSE.sav | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'testbench/PAUSE.sav')
| -rw-r--r-- | testbench/PAUSE.sav | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/testbench/PAUSE.sav b/testbench/PAUSE.sav new file mode 100644 index 000000000..f5e1ea1ac --- /dev/null +++ b/testbench/PAUSE.sav @@ -0,0 +1,62 @@ +[size] 1400 967 +[pos] -1 -1 +*-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] u2_sim_top. +[treeopen] u2_sim_top.u2_basic. +[treeopen] u2_sim_top.u2_basic.MAC_top. +[treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx. +@22 +u2_sim_top.GMII_TXD[7:0] +@28 +u2_sim_top.GMII_TX_EN +@200 +- +@24 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk +@24 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1 +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1 +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en +u2_sim_top.u2_basic.proc_int +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] +@25 +u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0] |