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author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:00:25 -0700 |
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committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:07:59 -0700 |
commit | 1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (patch) | |
tree | 04f94ef4f7f06a210f7532592829332c7f2621f0 /simple_gemac/simple_gemac_rx.v | |
parent | 7b8f65256b5ea300187ebb6a359df2fa707a295d (diff) | |
parent | 42fc55415af499980901c7787f44c7e74b4a9ce1 (diff) | |
download | uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.gz uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.bz2 uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.zip |
Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
...
Diffstat (limited to 'simple_gemac/simple_gemac_rx.v')
-rw-r--r-- | simple_gemac/simple_gemac_rx.v | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/simple_gemac/simple_gemac_rx.v b/simple_gemac/simple_gemac_rx.v index 7daa9adad..45ddd6dfa 100644 --- a/simple_gemac/simple_gemac_rx.v +++ b/simple_gemac/simple_gemac_rx.v @@ -1,14 +1,31 @@ module simple_gemac_rx - (input clk125, input reset, + (input reset, input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD, output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack, input [47:0] ucast_addr, input [47:0] mcast_addr, input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all, output reg [15:0] pause_quanta_rcvd, output pause_rcvd ); - reg [7:0] rxd_d1; + localparam RX_IDLE = 0; + localparam RX_PREAMBLE = 1; + localparam RX_FRAME = 2; + localparam RX_GOODFRAME = 3; + localparam RX_DO_PAUSE = 4; + localparam RX_ERROR = 5; + localparam RX_DROP = 6; + + localparam RX_PAUSE = 16; + localparam RX_PAUSE_CHK88 = RX_PAUSE + 5; + localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1; + localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1; + localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1; + localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1; + localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1; + localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1; + + reg [7:0] rxd_d1; reg rx_dv_d1, rx_er_d1; assign rx_clk = GMII_RX_CLK; @@ -19,13 +36,18 @@ module simple_gemac_rx rxd_d1 <= GMII_RXD; end + reg [7:0] rx_state; wire [7:0] rxd_del; wire rx_dv_del, rx_er_del; reg go_filt; + wire match_crc; + wire clear_crc = rx_state == RX_IDLE; + wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1; + localparam DELAY = 6; delay_line #(.WIDTH(10)) rx_delay - (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_dl,rxd_del})); + (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del})); always @(posedge rx_clk) if(reset) @@ -37,7 +59,6 @@ module simple_gemac_rx wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | (pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all; - reg [7:0] rx_state; assign rx_data = rxd_del; assign rx_error = (rx_state == RX_ERROR); @@ -58,24 +79,6 @@ module simple_gemac_rx address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1), .address(48'h0180_c200_0001), .match(is_pause), .done()); - localparam RX_IDLE = 0; - localparam RX_PREAMBLE = 1; - localparam RX_FRAME = 2; - localparam RX_GOODFRAME = 3; - localparam RX_DO_PAUSE = 4; - localparam RX_ERROR = 5; - localparam RX_DROP = 6; - - localparam RX_PAUSE = 16; - localparam RX_PAUSE_CHK88 = RX_PAUSE + 5; - localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1; - localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1; - localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1; - localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1; - localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1; - localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1; - - always @(posedge rx_clk) go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5); @@ -155,9 +158,6 @@ module simple_gemac_rx endcase // case (rx_state) assign pause_rcvd = (rx_state == RX_DO_PAUSE); - wire match_crc; - wire clear_crc = rx_state == RX_IDLE; - wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1; crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc), .data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc)); |