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| author | Matt Ettus <matt@ettus.com> | 2009-10-01 01:02:25 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-10-01 01:02:25 -0700 |
| commit | 42fc55415af499980901c7787f44c7e74b4a9ce1 (patch) | |
| tree | ffefbf0e212d5ad895b1a391e9e4b5fb21c74283 /serdes | |
| parent | 0a0655b56b84aa6557cdfaece206d0f5cf6ebeac (diff) | |
| download | uhd-42fc55415af499980901c7787f44c7e74b4a9ce1.tar.gz uhd-42fc55415af499980901c7787f44c7e74b4a9ce1.tar.bz2 uhd-42fc55415af499980901c7787f44c7e74b4a9ce1.zip | |
Fix warnings, mostly from implicitly defined wires or unspecified widths
Diffstat (limited to 'serdes')
| -rw-r--r-- | serdes/serdes_tx.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v index c74414e92..2e5e3bd80 100644 --- a/serdes/serdes_tx.v +++ b/serdes/serdes_tx.v @@ -84,7 +84,7 @@ module serdes_tx wire rd_eop_i = rd_flags_i[1]; wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused - wire have_data, empty; + wire have_data, empty, read; fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo (.clk(clk),.reset(rst),.clear(0), .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o), |