seems to build a decent fpga, but still some issues with a full connection.

2 files changed, 33 insertions, 26 deletions

diff --git a/sdr_lib/rx_control.v b/sdr_lib/rx_control.v
index ae821e822..0adeb0794 100644
--- a/sdr_lib/rx_control.v
+++ b/sdr_lib/rx_control.v
@@ -63,22 +63,17 @@ module rx_control
       .read(read_ctrl), .empty(empty_ctrl) );
 
    // Buffer interface to internal FIFO
-   wire    write, full, read, empty;
-   wire    sop_o, eop_o;
-   assign wr_flags_o  = {2'b00, eop_o, sop_o};
-   assign wr_ready_o  = ~empty;
-   assign read = wr_ready_i & wr_ready_o;
-   
-   wire [33:0] fifo_line;
+   wire        have_space, write;
+   wire [35:0] fifo_line;
    
    // Internal FIFO, size 9 is 2K, size 10 is 4K
-   cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo
-     (.clk(clk),.rst(rst),.clear(clear_overrun),
-      .datain(fifo_line), .write(write), .full(full),
-      .dataout({sop_o,eop_o,wr_dat_o}), .read(read), .empty(empty),
+   fifo_cascade #(.WIDTH(36),.SIZE(FIFOSIZE)) rxfifo
+     (.clk(clk),.reset(rst),.clear(clear_overrun),
+      .datain(fifo_line), .src_rdy_i(write), .dst_rdy_o(have_space),
+      .dataout({wr_flags_o,wr_dat_o}), .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i),
       .space(),.occupied(fifo_occupied) );
-   assign      fifo_full = full;
-   assign      fifo_empty = empty;
+   assign      fifo_full = ~have_space;
+   assign      fifo_empty = ~wr_ready_o;
 
    // Internal FIFO to DSP interface
    reg [22:0] lines_left;
@@ -133,13 +128,13 @@ module rx_control
 	     else if(too_late)
 	       ibs_state <= IBS_OVERRUN;
 	   IBS_FIRSTLINE :
-	     if(full | strobe)
+	     if(~have_space | strobe)
 	       ibs_state <= IBS_OVERRUN;
 	     else
 	       ibs_state <= IBS_RUNNING;
 	   IBS_RUNNING :
 	     if(strobe)
-	       if(full)
+	       if(~have_space)
 		 ibs_state <= IBS_OVERRUN;
 	       else
 		 begin
@@ -165,21 +160,21 @@ module rx_control
 		      end
 		    else
 		      lines_left_frame <= lines_left_frame - 1;
-		 end // else: !if(full)
+		 end // else: !if(~have_space)
 	 endcase // case(ibs_state)
    
-   assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {1'b1,1'b0,master_time} :
-		      {1'b0,((lines_left==1)|(lines_left_frame==1)),sample};
+   assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {2'b0,1'b0,1'b1,master_time} :
+		      {2'b0,((lines_left==1)|(lines_left_frame==1)),1'b0,sample};
    
-   assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & ~full;  // & (ibs_state == IBS_RUNNING) should strobe only when running
+   assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & have_space;  // & (ibs_state == IBS_RUNNING) should strobe only when running
    assign overrun = (ibs_state == IBS_OVERRUN);
    assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE);
    assign read_ctrl = ( (ibs_state == IBS_IDLE) | 
-			((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) )
+			((ibs_state == IBS_RUNNING) & strobe & have_space & (lines_left==1) & chain) )
 	  & ~empty_ctrl;
    
    assign debug_rx = { 8'd0,
-		       1'd0, send_imm, chain, wr_ready_i,wr_ready_o, eop_o, sop_o, run,
-		       write,full,read,empty,write_ctrl,full_ctrl,read_ctrl,empty_ctrl,
+		       1'd0, send_imm, chain, wr_ready_i,wr_ready_o, 2'b0, run,
+		       write,have_space,wr_flags_o[1:0],write_ctrl,full_ctrl,read_ctrl,empty_ctrl,
 		       sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] };
 endmodule // rx_control
diff --git a/sdr_lib/tx_control.v b/sdr_lib/tx_control.v
index 8766afd8b..e5fed0b93 100644
--- a/sdr_lib/tx_control.v
+++ b/sdr_lib/tx_control.v
@@ -64,22 +64,34 @@ module tx_control
 	     if(rd_eop_i)
 	       xfer_state <= XFER_IDLE;
 	 endcase // case(xfer_state)
+
+   wire have_data_space;
+   assign full_data   = ~have_data_space;
    
-   assign write_data = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o;
-   assign write_ctrl = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o;
+   assign write_data  = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o;
+   assign write_ctrl  = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o;
 
-   assign rd_ready_o = ~full_data & ~full_ctrl;
+   assign rd_ready_o  = ~full_data & ~full_ctrl;
    
    wire [31:0] data_o;
    wire        eop_o, eob, sob, send_imm;
    wire [31:0] sendtime;
    wire [4:0]  occ_ctrl;
-   
+/*   
    cascadefifo2 #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo
      (.clk(clk),.rst(rst),.clear(clear_state),
       .datain({rd_eop_i,rd_dat_i[31:0]}), .write(write_data), .full(full_data),
       .dataout({eop_o,data_o}), .read(read_data), .empty(empty_data),
       .space(), .occupied(fifo_occupied) );
+*/
+   wire        have_data;
+   assign empty_data  = ~have_data;
+   
+   fifo_cascade #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo
+     (.clk(clk),.reset(rst),.clear(clear_state),
+      .datain({rd_eop_i,rd_dat_i[31:0]}), .src_rdy_i(write_data), .dst_rdy_o(have_data_space),
+      .dataout({eop_o,data_o}), .src_rdy_o(have_data), .dst_rdy_i(read_data),
+      .space(), .occupied(fifo_occupied) );
    assign      fifo_full = full_data;
    assign      fifo_empty = empty_data;