Merged SVN matt/new_eth r10782:11633 into new_eth

* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth
  -r10782:11633

* Patch applied with no conflicts or fuzz.

1 files changed, 9 insertions, 37 deletions

diff --git a/sdr_lib/rx_control.v b/sdr_lib/rx_control.v
index d41a28bcf..ae821e822 100644
--- a/sdr_lib/rx_control.v
+++ b/sdr_lib/rx_control.v
@@ -9,15 +9,12 @@ module rx_control
      input [31:0] master_time,
      output overrun,
      
-     // To Buffer interface
+     // To FIFO interface of Buffer Pool
      output [31:0] wr_dat_o,
-     output wr_write_o,
-     output wr_done_o,
-     output wr_error_o,
-
+     output [3:0] wr_flags_o,
      input wr_ready_i,
-     input wr_full_i,
-     
+     output wr_ready_o,
+
      // From DSP Core
      input [31:0] sample,
      output run,
@@ -68,35 +65,10 @@ module rx_control
    // Buffer interface to internal FIFO
    wire    write, full, read, empty;
    wire    sop_o, eop_o;
-
-   reg 	   xfer_state;
-   localparam XFER_IDLE = 1'b0;
-   localparam XFER_GO = 1'b1;
-
-   always @(posedge clk)
-     if(rst)
-       xfer_state <= XFER_IDLE;
-     else
-       if(clear_overrun)
-	 xfer_state <= XFER_IDLE;
-       else
-	 case(xfer_state)
-	   XFER_IDLE :
-	     if(wr_ready_i)
-	       xfer_state <= XFER_GO;
-	   XFER_GO :
-	     if((eop_o | wr_full_i) & wr_write_o)
-	       xfer_state <= XFER_IDLE;
-	   default :
-	     xfer_state <= XFER_IDLE;
-	 endcase // case(xfer_state)
+   assign wr_flags_o  = {2'b00, eop_o, sop_o};
+   assign wr_ready_o  = ~empty;
+   assign read = wr_ready_i & wr_ready_o;
    
-   assign     wr_write_o = (xfer_state == XFER_GO) & ~empty;
-   assign     wr_done_o = (eop_o & wr_write_o);
-   assign     wr_error_o = 0;   // FIXME add check here for eop if we have wr_full_i once we have IBS
-
-   assign     read = wr_write_o | (~empty & ~sop_o);   // FIXME  what if there is junk between packets?
-
    wire [33:0] fifo_line;
    
    // Internal FIFO, size 9 is 2K, size 10 is 4K
@@ -206,8 +178,8 @@ module rx_control
 			((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) )
 	  & ~empty_ctrl;
    
-   assign debug_rx = { 6'd0,send_imm,chain,
-		       wr_write_o, wr_done_o, wr_ready_i, wr_full_i,xfer_state,eop_o, sop_o, run,
+   assign debug_rx = { 8'd0,
+		       1'd0, send_imm, chain, wr_ready_i,wr_ready_o, eop_o, sop_o, run,
 		       write,full,read,empty,write_ctrl,full_ctrl,read_ctrl,empty_ctrl,
 		       sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] };
 endmodule // rx_control